BGAs jump speed/density barrier

BGAs jump speed/density barrier
The combination of large, complex devices with hundreds of pins and densely packed system layouts has led to the proliferation of ball grid array packages. Once the domain of a few specialized devices in very high-end equipment, these package types are making their way into everything from datacom and telecom switches to portable computers.

Techniques for building layouts around BGAs are more involved and more complex than for standard surface-mount devices. However, these packages allow for a layout that optimizes board space, and they can actually improve electrical characteristics over comparable packages.

For absolute maximization of space, a tighter-and therefore more precise-layout is required. As a standard rule of thumb, the number of board signal layers required is equal to the number of ball rows on the BGA package minus one. That makes it easier for the package designer to route the two outer ball rows to the outside of the package, and the two interior rows to the center space beneath the BGA package. Ball rows that are situated farther in than the outer or inner two rows generally require vias for access.

The ball pitch of most BGA packages is actually greater than in comparable SMT packages. This increases line spacing, which decreases coupled noise and crosstalk effects. But the speed of communications devices will force layout engineers to pay attention to trace lengths and coupling effects.

Precision routing is critical to clean signals, especially as speeds rise. In general, the same good signal integrity techniques used for other package and board layouts apply for BGAs. Trace lengths must be matched to minimize skew. To minimize reflections, designers must avoid T-junctions and stubs.

Vias have inherent capacitance and inductance characteristics directly related to their physical size. Capacitance is proportional to via diameter, and inductance is proportional to via length. That is, capacitance increases as via diameter does, and inductance increases with via length.

As frequencies rise, smaller and shorter vias to reduce capacitance and inductance become more crucial to clean signal behavior. The trade-offs here, of course, are cost vs. diameter and length. Smaller diameters require smaller drill bits or lasers, and shorter lengths mean blind, buried or micro vias.

It would be difficult to include too many decoupling capacitors for a high-pin-count BGA. Because of their size and complexity, the devices require an extensive amount of decoupling to operate with as little power and switching noise as possible.

Using a minimum of one small decoupling capacitor for every two power pins-typically 0.1 up to 0.7 microfarad-along with several large bulk capacitors is considered a minimum requirement for many large devices. However, the device vendor can supply exact recommendations, since power requirements and frequency of operation have the most impact on decoupling requirements.

With most BGA devices, small decoupling capacitors can be placed directly underneath the device next to the pins for which they provide decoupling. This is the optimum design, both from a decoupling and a board-usage perspective.

If under-device mounting is not possible, mounting on the opposite side of the board beneath the center of the package is an option. The bulk capacitors can also be placed on the opposite board side, under the center of the device.

Alternatively, the decoupling capacitors can be placed on the same board side as the device, provided the traces to the power pins can be kept short.

To achieve a more-compact layout, it may be possible to reduce all ball rows to board signal layers minus two. To accomplish that, a careful and precise layout is necessary. Via layout also requires a good deal of forethought. A row of closely spaced vias can act as a plane cut for every layer they pass through. This can be especially problematic for ground and power layers, which require a "safety zone" space around any vias passing though that layer. If adjacent vias are too close, no copper will be filled in between them. This can result in no power and ground plane connections under the BGA device-or just very thin strips between the center of the device and the rest of the ground and power planes. In either case, susceptibility to power fluctuations and signal noise can result.

Layout problems
To prevent these problems, the layout engineer must ensure that the BGA layout incorporates several wide, via-free channels that allow ground and power plane connection to the center of the device.

Fortunately, there are multiple via types, dramatically increasing the options for BGA layout. However, all of these via types have trade-offs in cost, manufacturing ease or use of board space. The most common is the through-hole via, drilled through the board after all layers are assembled. This via type is the least expensive to implement and allows the easy connection of discrete components such as decoupling capacitors on the reverse side of the board. Drawbacks include the amount of board real estate these vias consume. As noted previously, an array of this type can create a "wall of vias" through every layer on the board, causing not only ground and power plane connection problems, but also potentially limiting the routing of signal traces on every layer. Additionally, these arrays can limit the placement of components on the reverse side of the board.

The increase in board and layout complexity has brought with it an increase in the use of blind and buried vias. These vias decrease the amount of board space "wasted" by connecting only the layers required. The blind via runs from one surface layer only to the layer required for connection. The buried via does not connect to either surface, linking only interior layers that need signal or power connection.

The drawback to these two options is the more complex and, therefore more costly, assembly process. Blind vias require drilling with a high degree of depth precision, and buried vias require prelayer assembly drilling.

Microvias, as the name implies, are very small, typically 4 micrometers. They are often laser-drilled, allowing connection to the next one or two board layers. The microvia's size gives it some advantages, especially in space-constrained layouts.

Because it's so small, a microvia can be used for via-in-pad connections. This eliminates the pad-to-via connection trace between balls. And the microvia also takes up significantly less layer space than a typical 0.254-mm (10-mil) via. As with blind and buried vias, however, the drawback to microvias is cost and manufacturing complexity.

Saving board space
Using microvias for via-in-pad, running to the first or second board layer, and connecting to a buried via to continue to additional layers if needed can save a significant amount of board space and ease routing of a high-pin-count BGA dramatically.

Indeed, BGA packages are not inherently more difficult than surface-mount packages to implement and lay out, provided you know the options and requirements for implementation. Depending on layout choices, assembly costs may be more than with an equivalent surface-mount package. Nonetheless, with careful layout, BGAs have benefits in less-exact assembly placement requirements, the potential for lower noise and crosstalk, and smaller overall system size.

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