CAD tackles package parasitics

CAD tackles package parasitics
RF and mixed-signal (RF-AMS) IC design is already very challenging today, without designers' having to worry about the electrical, thermal and yield effects of the chip package. The package essentially adds parasitic resistive, inductive and capacitive effects to the system performance. Those RLC effects need to be captured in the IC and electrical-package design flows.

For example, in silicon germanium power amplifier design, the electrical properties of the package are critical to whether the product will provide enough gain to meet specification. It is important to understand the CAD issues that the package imposes on RF and mixed-signal system-on-chip (SoC) designers. Part of the job involves a detailed analysis of parasitic effects in IC design.

There are two types of IC parasitics that RF and mixed-signal (RF-AMS) designers seem to worry most about: the interconnect and the substrate. For each of those, there are numerous tools available from EDA vendors, some integrated into the design framework and some suitably accurate.

A generic RF-AMS IC design flow would include pointers to a package modeler that would portray IC parasitic effects. In any design flow, the parasitics need to be modeled early in the cycle-in the schematic design, in fact-for critical nets, using transmission line models and substrate isolation between blocks, as well as in the physical design and during physical verification. If those items are to be useful to the designer, they need to be highly accurate, ideally based on and even correlated to the silicon process being used. The models also need to be sufficiently integrated into the design methodology so that issues such as the transmission lines in the interconnects are recognized in the layout and physical verification steps.

Package parasitics can be extracted and modeled using any number of tools, from 3-D RLC extraction products to S-parameter modeling tools. Both of those approaches have their advantages and disadvantages. Typically, models for S-, or scattering-, parameter-including amplitude and phase relationships, resulting incident and reflection waves-describe the behavior of a device under linear conditions at microwave frequency range. S-parameters are more accurate but take longer to simulate in transient (time-domain) simulations, and many IC Spice simulation tools are not set up to import or support them. Conversely, the RLC models can be inaccurate at high frequencies as well slow to simulate when mutual parasitics are being modeled-especially mutual inductance. Thus, the package design and model can change throughout the IC design flow.

The final package design is dependent on the effect the package will have on the IC product's performance and may vary as the IC design progresses. For example, in power amplifier design for wireless systems, the package model needs to be co-designed with the IC design. That leads to a need for a series of co-simulations, involving both the IC and the package, during their mutual design process.

But few tool methodologies address this requirement effectively, primarily because vendors propose only their own tools in their published reference CAD flows. Thus the design house needs to carefully scope the tools requirements and build the needed flows.

From there, a design process is needed that coordinates both the package and IC design flow processes.

For mixed-signal SoC designs- where multiple mixed-signal intellectual-property blocks (data converters, phase-locked loops, serdes devices) and digital IP blocks (DSPs, microprocessors, memories) are integrated rapidly together-parasitic modeling is at difficult at best.

Noise issues
The Virtual Socket Interface Alliance ( .vsi.org) has started to address that issue and has recently released a technical document to help IP authors and integrators work through the parasitic-noise issues in SoC designs more effectively. Unlike RF-AMS designs, mixed-signal SoC designs are usually less sensitive to the effects of the package. But more-sensitive RF and analog circuitry can be integrated with the recent introduction of advanced passive devices in RF-CMOS processes. And that naturally points back to higher sensitivity to the package parasitics.

Decisions in mixed-signal SoC design are typically driven by cost and, therefore, the need for cheap packages. That, in turn, leads to limited pin allocation for grounding of the substrate and mixed-signal circuit blocks. Pin allocation is a difficult topic to deal with, beyond the issue of parasitic noise. But the strength of the dc and ac ground networks is known to be key to noise minimization, so the more grounding pins available, the better.

For peripheral I/O packages such as leaded packages-typically where pin congestion occurs-the inductance may be as much as 0.5 to 1 nanohenry. That's enough to cause circuit noise issues at high frequencies. Conversely, for area I/O flip-chip packages, like bumped die or ball grid arrays, congestion in mixed-signal SoC designs is not such a bottleneck. Thermal issues may arise, however, in high-frequency custom digital serial links, and the I/O images often need to be customized to avoid unnecessary bump capacitance in the critical signal or clock path.

While there are no easy answers, the choice of package can be influenced by numerous factors. For example, if the IC design is being migrated from a previous product that used a peripheral I/O package, then moving to an area I/O design may turn out to affect the design schedule significantly. This is especially risky if the design team has no experience in area I/O and does not understand the issues being faced.

Co-design of the package and IC is a well-practiced methodology that RF designers have followed for years. For mixed-signal SoC design, the package design is still important, but lower cost is often a far higher priority, and a standard high-yield-and therefore cheap-part is king.

Looking to the future, there may be a time when RF-AMS SoC devices emerge; one example is GSM IP mixed with DSPs and microprocessors. That will lead to greater design challenges, but it's worth noting that the packaging technology will also have improved.

The best advice is to start with an experienced design and CAD team.

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