IC packaging raises modeling, layout concerns in communications design

IC packaging raises modeling, layout concerns in communications design
IC packaging, typically an afterthought in the design of a new-generation SoC, is particularly troublesome for communications circuits and high-speed interface circuits. Everyone wants small size and low heat dissipation in their RF transceiver or network interface circuits. Everyone would use a bumped die or some kind of chip-scale package, if they could. The problem is there are too many pins.

Tiny packages with high-density I/O and ultra-narrow pin spacing create two types of engineering problems: One is the increased probably of noise, crosstalk and signal integrity issues. Narrow pin-spacing between high-speed signal lines create the possibility that signals from one line will bleed through to an adjacent line — what signal integrity experts are starting to call interactions between "aggressors" and "victims." This increase in noise can result in false logic triggers. Often, its typical effect is a decrease in data transmission rates, as the receiver circuitry must utilize more complex error correction techniques to digitally reconstruct a signal messed by sloppy packaging.

The other contingency is more complicated pc board layouts. The issue is not only fine-pitch routing; it is also in multiplayer pc boards. As contributor Sean Clark of Fairchild's Integrated Circuits Group points out in his article, the number of pc board layers must be roughly equivalent to the number of pin-rows on your BGA to ensure that all signals lines have a place to go; that is, to insure the I/O can be properly routed — no mean feat if you've got a BGA with 792 pins.

Thus, like SoC design, IC packaging is thrown into an early alliance with EDA tools in an effort to understand the signal integrity penalties imposed by high-density, high-pin counts and high speeds on one hand, and to affect an ultra-precise pc board layout and trace routing on the other.

Contributors to this week's InFocus offer their views on high density IC packaging challenges starting with IBM Microelectronics' Raminderpal Singh, who co-chairs the AMS working group in the Virtual Socket Interface Alliance (VSIA) — their go-to-guy on signal integrity issues. In his contribution, Singh emphasizes the importance of modeling the effects of package design through the design cycle of communications, RF or mixed-signal IC. He identifies places where the modeling of wirebonds, leadframes and other IC package interconnects would make sense . He does acknowledge that many users will experience package modeling as a "start-stop-model-start-stop-again" process in an IC design flow. Designers keep hoping the process will be more integrated and coherent.

Meanwhile, other contributors discuss their experiences with particular package types — ball grid arrays (BGAs), most prominently.

Analog Devices' principal engineer, Roy Buck, for example, is a partisan for multichip modules (MCMs). Essentially, a module package, made up of several chips and matching passives, comes to market faster than an SoC. A multi-layer printed circuit board on a BGA platform will compete with low-temperature co-fired ceramics (LTCC) in terms of cost, Buck notes, but RF performance will be contingent on the rigidity of the substrate material. Thus, the material used (a complex resin) will require more attention than the FR4 materials used for lower-frequency packages.

Fairchild's Sean Clark deals with the issue of high-pin count communications ICs. Crosspoint switches are a necessary item for high-speed networking: switch matrices connect inputs to any variety of outputs. I-Cube, a company now under Fairchild's umbrella, had developed the MSX532, a 256 port by 256 port switch matrix, with differential connections - two lines per port - to ensure signal integrity. By using internal SRAMs to buffer the connections, I-Cube was able to reduce the complexity of the connection matrix. Still, the MSX532 — a device with 532 I/Os, clocks and control lines — is a BGA with 792-pins. In his contribution, Clark provides a tutorial on working with high-pin count devices.

And, package designer Frank Juskey of Advanced Interconnect Technologies (Pleasanton, Calif.) offers some advisories on increasingly popular chip-scale packaging. They are extremely useful in applications with only a small number of I/O pins, Juskey points out, but the choice of interconnects (like folded leads) can be significant for noise and crosstalk in high-speed applications. The quad flat no leads (QFN) package provides an alternative for the noisy leadframes often used with chip-scale packaging.