QFN packages quell noise, cost, space in handhelds

QFN packages quell noise, cost, space in handhelds
One of the most cutting-edge packaging technologies to recently emerge in the electronics marketplace is the quad flat no leads (QFN)-type package. It serves as an alternative to the more costly laminate-based chip scale packages (CSP) the fine-pitch ball grid array (FBGA), the flex ball grid array (FxBGA) and micro BGA in portable applications, such as cellular handsets and PDAs. The QFN-type package is known for its small size, cost-effectiveness and good production yields.

QFN-type packages are performance and efficiency competitive with array packages including the FBGA because they to do not require ball grid array (BGA) substrates, and do not require expensive ball tooling. They are best used in low-lead count arrays. Leaded packages in the same form factors include small outline integrated circuits (SOIC) and thin shrink small outline packages (TSSOP). QFN-types include very fine pitch quad flat pack-no leads (VFQFP-N) and very very fine pitch quad flat pack-no leads (WFQFP-N).

QFN-type packages also possess certain mechanical advantages for high-speed circuits including improved co-planarity and heat dissipation. Because QFN packages do not have gull wings leads which at times can act as antennas, creating "noise" in high-frequency applications, their electrical performance is superior to traditional leaded packages.

In addition, they provide excellent thermal performance through the exposed leadframe pad, which enables a direct thermal path for removing heat from the package. This thermal enhancing feature can be further taken advantage of when the package leadframe pad is soldered to the board.

The small footprint of the QFN-type package, coupled with the low mounted height and good moisture performance, has quickly gained acceptance in the marketplace. In addition, the QFN-type package can be easily reeled for placement in standard surface mount (SMT) equipment, as used in traditional leaded packaging technologies, and the high contrast between the pads and body enable easy alignment by the equipment's vision system. Since these devices are typically less than 14 mm on one side, no special SMT placement equipment is required, translating to a considerable cost savings for second level assemblers.

Another benefit of laminate-based packages, when compared BGA packages, is their ability to offer higher density interconnects than that in standard leadframe packages. This is due to the laminate's ability to arrange its I/O's in an array or grid rather than solely in a peripheral arrangement. The QFN-type package combines the best of both worlds in which the leads can be placed in single-, dual- or triple-wiring rows to enable increased functionality in a single package, which translates into lower costs. QFN-type packages also take advantage of the fact that leadframe based packaging is lower in cost than laminate based offerings because it is less expensive to simply etch a thin piece of copper than to fabricate a pc board through many costly manufacturing steps.

An additional benefit is the exposed die flag. When soldered to a motherboard, the exposed die flag offers a heat conduit for thermal relief that enables very high power die, such as that in a power amplifier (PA), to be packaged in this type of device. PAs are used extensively in cell phones, and take advantage of the QFN soldered die flag to dissipate considerable thermal energy with a minimal inductive coupling to the surrounding circuitry.

Harnessing flip chip
A need exists for both wire bond and flip chip versions of the QFN-type packages. The flip chip version offers a new dimension in today's packaging technology. Advanpack Solutions, Ltd . (APS), based in Singapore, offers a die pillar bumping process that approaches wire bond costs. When this technology is combined with the QFN, the density of a BGA-type of product can be obtained at very attractive cost. The electrical properties of the flip chip version of a QFN-type far surpass those of the wire-bonded version. This provides designers of high frequency or fast clock speed devices with a package that can provide the level of electrical performance needed by the new generation of electronic devices.

Since the flip chip version of the QFN-type package requires fewer process steps and fewer pieces of capital equipment, the process flow is shorter and the work-in-progress (WIP) is less, translating directly into an improved manufacturing process. There is no gold wire, die attach or selective plating on the leadframes; thus the manufactured part normally exhibits an improved mechanical reliability due to fewer failure prone interfaces.

Current manufacturing technology allows for a 100 micron bump (65 microns of plated copper and 35 microns of eutectic tin/lead) on pitches as low a 200 microns. Developmental work continues and has been able to achieve pitches as fine as 180 microns. The APS bumping process effectively seals the die bond pads from the environment by overplating the die pad opening. The large standoff of the die surface from the eutectic solder cap produces an excellent buffer from "soft" errors caused by the close proximity of alpha particles from the lead (Pb) in most conventional solder bumping techniques. The most notable benefit of the QFN-type flip chip version is the standoff from the lead frame and the reduced pitch. This also enables a dramatic reduction in the package height.

The combination of the flip chip configuration and the etched leadframe used in the manufacture of QFN-type package offers multiple rows of leads, increased wiring density, with more wires per square inch.

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