Flexible timing key to CCD design

Charge-coupled devices (CCDs) are the image sensor of choice for digital imaging applications. The exploding demand for products like digital still cameras and digital camcorders has made the CCD familiar to everyday consumers. The volume of digital still cameras has been growing at the rate of more than 40 percent a year, with total shipments in 2002 expected to reach approximately 20 million units. This staggering volume has contributed to a decrease in the average price of a CCD, making digital imaging products more affordable. But it has also increased the challenge for the designer to develop a product that distinguishes itself from the myriad others in the market.

Compounding this challenge, much of a CCD sensor's functionality and performance depend wholly on another component: the timing generator, which produces a variety of clock pulses. The pulses drive charges accumulated in the CCD's pixel array to a signal-conditioning circuit, where they can be digitized and then processed into an image. The clock pulses determine how the image is acquired and reconstructed (as a still or moving image), so the timing generator is a key component in the imaging signal chain.

Whether the CCD is used in consumer, scientific or industrial imaging fields, the market dictates the resolution and performance needed of the CCD in the application. As such, the designer has a relatively limited selection of CCD imagers from which to choose. Also, since competitors are likely to use similar (or identical) sensors, the innovative designer has almost no flexibility in differentiating his design through the CCD if the accompanying timing generator functionality is fixed. In other words, the designer is limited to what he can actually do with the CCD as an image sensor, due to the lack of flexibility in the timing generator. Most high-resolution CCDs-those with more than a million pixels-are targeted at the consumer imaging market. That makes it especially challenging for designers in the scientific and industrial imaging fields, since these fixed-function timing generators will not be designed with their specific needs in mind.

Several other issues exist with the fixed-function, discrete timing generator. In many cases, the designer may have to introduce a rapid succession of products in series, each with a different CCD. It would obviously help to use a standardized design, with the same components and pc-board layout as much as possible. With fixed-function timing generators, standardization of the analog front-end portion (AFE) of the design would not be possible because a different timing generator would be needed for each CCD. This, in turn, would necessitate a new design and layout for each application. The latter is especially critical and time-consuming in a high-speed, highly sensitive imaging application.

The discrete timing generator, separated from the analog front end and CCD, produces high-speed clocks that increase the likelihood of digital crosstalk and create electromagnetic interference (EMI) shielding issues in sensitive image systems. External shielding materials and design layout are needed to counteract these effects, both to maintain performance specifications and to satisfy EMI regulations.

The fixed-function timing generator is typically the same size as the analog front end, both frequently packaged in 48-pin thin quad flat packs (TQFPs). In space-sensitive applications, these two chips would take up much precious board space.

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Fixed-function timing generators are susceptible to temperature-induced timing variability, which adversely affects image quality by the subtle shift in edges of sampling clocks. This can be unacceptable in many situations, since users expect higher-resolution, higher-performance imaging systems that are stable over a wide range of environmental conditions. In all of those cases, resolving the issues results in time-consuming changes to the system design and layout. Those changes subsequently lead to rising development costs and delays in product introduction.

An integrated, programmable timing generator can resolve all of the problems. The programmable timing generator is flexible enough for the designer to configure the timing specifications to the type of CCD the

application requires. That lets the designer program specific sequences that were not present on the standard, fixed-function timing generator, in turn allowing innovative functions not previously imagined and maximizing the overall performance of the CCD. Thus, the designer can more easily differentiate an application, even if the same image sensor was used in a competing product.

In addition, a programmable timing generator allows CCD imagers of differing resolutions to be obtained from a variety of manufacturers and used with the same printedcircuit board, since the timing generator can be configured, via software changes, to the timing specification that the CCD requires. That greatly reduces development time and expense, since much of the work needed to lay out and build the circuit boards with a discrete, fixed-function timing generator is eliminated.

In addition, the integration of a correlated double sampler, a programmable-gain amplifier and a 10- or 12-bit analog-to-digital converter and the timing generator will greatly reduce the presence of high-speed clocks on the circuit board. That significantly lowers the incidence of digital crosstalk between high-speed signals .

The standard benefit of monolithic integration applies to the integrated timing generator as well: a reduction in board space, which is a critical factor in portable applications like digital still cameras. For the integrated, programmable timing generator, the benefits of integration complement the advantages of flexibility, making it an ideal component for imaging applications.

Analog Devices recently introduced the first in a series of high-performance analog front ends, combined with a programmable timing generator. The AD9891 combines an analog front end, based on the AD9841A, with a programmable timing generator that uses the proprietary Precision Timing core architecture. The core lets the timing generator precisely control all of the clocks necessary to drive a CCD and enables the precise control of frame and pixel placement, shutter timing and other critical imaging functions. It is also robust enough to remain stable within a wide range of temperatures, assuring designers that performance will be maintained regardless of changing external conditions.

The programmable timing generator and its ability to manifest the creative innovations of designers will become the standard in the market, displacing traditional, fixed-function partitioning in imaging architectures.