Analog pre-processor boosts signal-to-noise ratios for digital cameras

Analog pre-processor boosts signal-to-noise ratios for digital cameras
In the recent years, the digital still camera changed status from a high-tech gizmo with limited performance to a valid alternative to the classic SLR single-lens reflex cameras. This change is made possible by the availability of cheap and fast image processing, the standardization of compression algorithms, the progress made in solid-state storage capacity, and the wide availability of high resolution imaging sensors.

To compete with chemical film, the promoters of the digital still camera concept had to drastically increase the number of sensing elements, or pixels, of the imaging sensor, from the mere 640x480 pixels of the first digital cameras to the 3, 4, 6 or even over 10 million pixels that can be found in the most high performing digital SLRs.

But to keep the cost of such sensors reasonable, while increasing the number of pixels, the size of these sensing elements had to be reduced proportionally, thus decreasing their sensitivity to light information, and increasing the effect of noise on the camera system performance. To limit the noise of the global system, which can degrade the image quality, but also the efficiency of compression algorithms, and thus the autonomy of the camera, one must take care to limit the noise in all the stages, from the light sensor to the digitization stage.

Thus, the camera system design demands careful attention to the front end signal processing and filtering elements. Up to now, CCDs (Charge Coupled Devices) have been the primary image sensor element, but, increasingly, high-resolution cameras are using CMOS image sensors with pixel sizes in the 6-to-9 um range. The devices which amplify the output of these sensors must have extremely low noise, yet the bandwidth of these stages must be kept large enough to allow for fast black-to-white transitions.

Integrated front-ends (also called analog pre-processors), which include the whole analog circuitry from the sensor output to the digital image processor input, have been used in mid-range consumer digital still cameras. The devices - many developed for digital camcorder applications - include a low-power 10-bit A-to-D converter, but only low signal bandwidth. The digital still cameras, used by professional photographers, artists and reporters - competing with SLR types - require higher bandwidth, low noise, and 12-bit resolution.

An analog interface that support high-resolution cameras (like Philips' TDA9965) includes a Clamp-and-Track and Hold Circuit, a Bandwidth Control Circuit, a 0-36 dB Programmable Gain Amplifier, and a 12-bit A-to-D Converter. All its functions, including the control pulses polarities selection, can be controlled via a serial 3-wire interface.

Image sensors usually output serially the image area video information, in an analog but time-discrete format (that is, as burst waveform). Moreover the useful video information is mixed with other contributions, such as reset noise, from which it must be extracted. Typically, the pixel output from a CCD is made of three parts, the reset pulse, which is useless for further processing, the floating diode level, which can serve as a kind of reference, and the pixel video content itself. To extract the relevant video information, a special filtering circuit must be used.

The Clamp-and-Track-and-Hold (CTH) circuit is an alternative to the Correlated-Double-Sampling (CDS) circuit usually found in consumer integrated front-ends. The CTH concept is used in some broadcast camera applications where its superior noise performance is absolutely needed. CMOS manufacturing allows its users to get the CTH advantages in an integrated front-end, for a modest cost and power consumption.

The CDS is used to sample each pixel at the floating diode level and the active video level, and to derive, by a simple difference, the actual pixel color information. The CTH principle uses a pixel clamp, which clamps the floating diode level to a known reference voltage, and then to sample directly the actual pixel color information. Thus the number of track & hold circuits, which is usually 3 or 5 for a standard CDS, can be reduced to one, thus also reducing potential noise sources.

Dynamic balance

The Bandwidth Controller is also a unique feature proposed by Philips. Using it allows the user to select dynamically the best balance between sharp transitions and low noise level. Its' low pass filter effect allows to compress the useful bandwidth of the signal, thus decreasing the noise integrated on the bandwidth. A side-effect of this choice is that the actual pixel transitions will be smoothed out, which can be a drawback for high-speed sensor applications, where the sensor output can vary in one pixel (i.e. 33ns for a 30 MHz pixel read-out rate) over 1Vpp or more.

It is advisable to adapt the CTH bandwidth to the actual read-out rate of the sensor. With a CTH control pulse width of 9ns, with the maximum bandwidth setting, the circuit is able to accurately process a black-to-white transition of 1Vpp with a precision of more than 99 percent. The Programmable Gain Amplifier ensures an optimal linearity and noise performance on the whole gain range, from 0 to 36dB. It can be set in steps of 0.05 dB via the serial interface. The A-to-D converter itself is a high-performance 12-bit one with a DNL of +/-0.9 LSB max (+/- 0.5 LSB typical).

The reference voltages used by a front end part like the TDA9965 are generated on-chip by a dedicated voltage regulator, which is powerful enough to drive several chips. An additional feature of the TDA9965 is that the regulator can be disabled, and an external reference used instead. This enables users to use up to four TDA9965 in parallel, using only one of the embedded voltage regulators to drive all the four circuits, thus limiting potential matching issues. This feature is especially useful in applications where sensors with several outputs are used. An init-on-power circuitry has also been implemented, which pre-charges all the clamp capacitors on power-on, in order to ensure a quick startup time, compatible with the use by sports photographers and photo-journalists.

The serial interface is a standard 3-wire one, suing the signals clock, data and enable. It is possible to control the AGC gain setting, clamp level, bandwidth limiter, as well as select the polarity of all the control pulses. The serial interface, as well as the clamp control inputs and all the high-speed clock inputs, are TTL compatible, and can thus interface seamlessly with both 5V and 3V micro-controllers and sensor timing generators.

The combination of these features result in a very flexible solution, with an extremely low noise performance, of 0.85 LSB at 0dB gain, and of only 6 LSB at 30 dB gain setting, giving at 30 dB gain an equivalent input noise of 45 µV (rms).

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