Decimation filtering key to ADSL data dissection

Decimation filtering key to ADSL data dissection
High-speed access to vast quantities of information pushed the development of broadband communication techniques. Today, more than 30 million subscribers use digital subscriber line services worldwide.

Generally, Internet users download far more information from a data source than they send back. Such asymmetry in the use of the communications channel led to the development of asymmetrical DSL technology. ADSL uses the present infrastructure of twisted copper pairs cables from the phone lines. It can share the same media with the voice channel so that the digital channels upstream and downstream are transmitted in different frequency bands.

The limitations of ADSL are related to the noise environment; crosstalk in the cable bundle at the source or at the subscriber ends; line attenuation; and the distance from the central office where the DSL access multiplexer (DSLAM) to the subscriber premises resides.

This technology can be thought as a frequency-division technique in that 256 digital modems at 64 kbits/second each are put in parallel to transport the required data rate, each operating into a frequency bandwidth of 4 kHz. If all channels are operational at the same time, the total bandwidth is 1.1 MHz, and the maximum data rate is 12 Mbits/s. At these rates, the distance from the central office to the customer is limited to 9,000 feet. Of the 256 parallel channels, one is used for voice (channel 0), 32 for upstream data (channels 1 to 31) and the rest for downstream data (32 to 256).

These transmission channels use discrete multitone transmission (DMT). The basic multicarrier transmission concept uses the basic tones (4 kHz) to divide the total data rate dynamically by allocating fractions of it to each of the particular tones in such a way that it adapts and matches to the best capacity of the given channel.

Most of the digital techniques for intersymbol interference and error correction are applied (trellis modulation/demodulation, forward error correction). The standards that govern the effective operation of ADSL include T1.413., ITU G.992.1 and ITU G.992.2 (ADSL lite). New standards are in preparation to help to reach customers at distances up to 18,000 feet from the central office or at higher data rates (VDSL). In terms of the protocol reference model, the Open System Interconnection (OSI) protocol still applies.

In the physical-media-dependent sublayer, the standards describe the line coupling, signal-filtering requirements, timing, time equalization, echo cancellation provisions, powering and protections. The physical-media-specific transmission convergence (PMS-TC) sublayer standards describe the framing operation requirements as well as scrambling and error monitoring. Finally, the transport-protocol-specific transmission convergence (TSP-TC) sublayer covers payload mapping and cell delineation.

In some cases, implementation of the standards requires filtering. Should the filters be implemented in hardware or calculated in a DSP? This is a system architecture question that guides hardware/software partitioning. Other design considerations include power dissipation, clock and data delays and layout constraints.

The filters can be used at different points in the signal-processing chain. Some of the filters, near the analog front end, are analog; the first is the subscriber line filter that separates the voice (telephony) from the upstream and downstream data (ADSL). Because the signal is analog in the analog front end, at some point it will be sampled and transformed into a digital signal. The filters that are encountered in the digital section are of special interest. But the simulation of the whole transmission chain can't be done without the characteristics of the analog filters.

The digital filters are, in most cases, linear filters of two types: infinite impulse response (IIR) and finite impulse response (FIR). These filters will be used subsequently to perform different functions necessary for the signal-processing chain.

Before entering the digital demodulator, the signal is adapted to the Nyquist data rate for the symbols in a data-rate reduction operation called decimation. The frequency of the symbols at the input of the decimator is 8.8 MHz. That is reduced to 2.2 MHz in the normal mode or 0.552 MHz in the reduced mode. The data is represented in two's complement in 16 bits.

3-stage implementation

The decimator is implemented in three stages. The first function is a linear windowing filter that calculates the output values through an averaging formula represented as a linear expression.

The internal processing, however, uses a higher number of bits (17/18) so that a noise-shaping feedback loop could be introduced in the data path that would modify the LSB side of the word. Because the word is represented in two's complement this also represents the noise-shaping function.

The windowing and the quasi-averaging operation affect the filter characteristics in the passband and stopband. And the arithmetic representation of the data plays an essential role in the implementation of the noise-shaping technique.

All this takes place at the first stage of the decimation filter. The second stage, called the halfband 16, is implemented using a FIR structure (or calculated into a DSP) for the expression being implemented as the function.

The filter coefficients c1,c3,.....,c(N-1)/2 are design-dependent and have been calculated into the design phase. They are are stored in the local memory (a lookup table) or in the general memory of the system.

The last stage, the halfband 4 module, is similar to the second stage but differs in the number of filter coefficients and their values.

Four types of DSP operators are required to implement these filters: adders, multipliers, time shift and control feedback loops. The designer's art consists of replacing the multiplier by a simple shift to the left operator and additioners, when that is possible. The DSP implementation does not require multiplier replacement, since the multiplier is part of the arithmetic unit, which performs the calculus. The data and coefficients are fetched from their memory locations. Those locations — prefetch, cache and lookup table — are all possible and are related to the design choices that are implemented in the particular design.

Another application for the digital filters is the time equalizer (TEQ), a FIR filter with programmable coefficients. Two coefficient tables (LUTs) are supported to allow for coefficient swapping on the DMT symbol boundary. The FIR filter computes 64 multiplications of the filter coefficients with the corresponding data samples. The coefficient word length (13 bits) differs from that of the samples(16 bits), so that the result is in 28 bits, a two's complement representation. A dc offset compensation takes place at this level. It is scaled appropriately, taking into account the size of the word. At the end of the operation, a 20-bit word is formed through the scaling/gain operation (6-dB steps).

Special features, such as saturation, are introduced and monitored in order to determine whether the TEQ is a saturated event. To understand the interesting part of this filter without entering into the function description, it is important to note that a filter has arithmetic properties. Thus the scaling of the operands before and after the operations should be implemented wisely.

Sometimes soft nonlinearities such as saturation are implemented in order to avoid divergence of the results. A flag should thus monitor the event in order to inform the front-end circuitry for scaling. This flag is used by post-processing.

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