Innovative ideas leap design hurdles at CICC

Innovative ideas leap design hurdles at CICC
The IEEE Custom Integrated Circuits Conference (CICC) has been the prime venue for new perspectives on the toughest problems facing integrated-circuit designers. This year's event, to be held this week in Orlando, Fla., offers a fresh crop of innovative circuit design ideas and exciting new approaches, some of which are excerpted in this week's In Focus section.

For example, embedded memory, which has become so important to the system-on-chip generation, has been simplified drastically in a new approach from researchers at Innovative Silicon Solutions (Le Landeron, Switzerland). The novel DRAM approach features a one-transistor cell with no capacitors and nondestructive read operations. A critical component for integrated systems is the use of an old standby — the MOSFET — as the storage cell. The pivotal concept is to use the floating-body effect made possible by a partially depleted silicon-on-insulator layer to store electrons or holes to represent logical 1s and 0s.

On the communications front, researchers at North Carolina State University (Raleigh) offer a fresh solution to the growing problem of interconnecting chips. They describe a 4-Gbit/second, high-density interconnection scheme that doesn't require physical connection. The design uses ac-coupled "buried solder bump" arrays based on current-mode signaling. The physical structure supports dc power and ground connections, and offers a simple mechanical interface

Project leader, Paul Franzon, professor in the Department of Electrical and Computer Engineering North Carolina State University, explains that the "structure allows for both dc connects and ac coupled paths — using capacitive coupled circuits or inductively coupled circuits — across the same interface and offers high density benefits and high data rates between ICs."

Franzon's background in micromachining as well as VLSI, helped inspire the new I/O scheme. The goal was to find a way to increase the density of connections to a VLSI chip using technology available today on fab lines, he explained. How do you get high density connect structures at a reasonable cost? This doesn't require special materials or processing. "You can do it with the materials and structures and manufacturing that are available today," he said. "High density chips, connectors and sockets all done at low cost. In the future, we see applying micromachining to other similar types of interconnect problems such as RF packaging."

The capacitively- coupled or inductively- coupled buried solder bump arrays create tens of thousands of I/Os. "You can use these for two purposes, for chips such as network processors that require a high number of I/O ports, or you can create more power and ground structures while keeping the current number of I/Os. This would be useful for dealing with noise management in computer chips," he said.

Another twist on the I/O problem - simply adding some FPGA-based buffers around the perimeter of a crossbar switch - has given Stanford University and NEC researchers the capability to boost the throughput of a network crossbar chip by as much as 100 percent. Called a flexiblecrossbar (Flexbar) the design exploits unused switching paths to provide additional data transfer capability for highly loaded paths.

"The crossbar has, for a long time, been the interconnect architecture of choice in a wide range of applications," said Anand Raghunathan, a senior researcher at NEC Research Labs, Princeton, NJ. "The exponential growth in communication bandwidth requirements, in applications such as network switches, is necessitating innovations in interconnect architectures. Our invention advances the performance achievable by crossbar-based switching fabrics with minimal hardware overheads."

"A limiting factor for the crossbar performance is usually the utilization, which is 50% or less under realistic traffic scenarios.," co-inventor Srivaths Ravi explains. "This observation inspired us to exploit unused switching resources by adding lightweight I/O layers to the switching fabric and the scheduler. Most research on improving switch performance has focussed on scheduling techniques; the Flexbar technology is unique in that it is complementary to these advances. The results are latency reductions of up to 70%, and doubles throughput for heavily loaded ports under various common traffic scenarios."

Meanwhile, engineers at Cypress MicroSystems Inc. (Bothel, Wash.) claim they have reached a new integration level for mixed-signal designs: the first mixed-signal field-programmable system-on-chip. The 24-MHz FPSOC integrates an 8-bit microcontroller, flash memory, SRAM, programmable analog and digital blocks, and on-chip clock generation. The interconnect allows analog and digital blocks to be combined to form a variety of functional modules.

Design engineer, Bert Sullam, explained that it is the first of its kind in the sense is that it has a combination of analog programmability and digital programmability along with programmable interconnect. "The target market is low cost microcontroller market. We are calling it a programmable chip — this is really equivalent to a microcontroller. The innovation is in the three types of programmability," he said.

And, engineers at Chipwrights,Inc., (Newton, Mass.) have come up with a system-on-chip containing a DSP with a vector architecture that can provide similar performance, cost and power to fixed DSP architectures. The architecture is fully programmable, permitting new classes of applications, shorter time-to-market and easy product differentiation for system integrators. The CW4011 exploits the parallelism typical of image processing to gain high performance at a low cost and low power.

"People had to this with fixed blocks — with our unit you can do it in a programmable way- cheap fast and low power," said John Redford, CTO for Chipwrights "We believe the architecture is an advance on how people do parallel architectures. The programmer doesn't have to think in parallel - this is a primary feature - people are daunted by that and the compiler is too. Essentially the hardware shields the programmer, and you can use the parallelism in a lot more places. We are bringing programmability at similar cost, power and performance."

For a list of contributed articles in this section, click here.