Ac scheme bumps I/O density

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Researchers are looking at a variety of methods to increase the density of interconnections. One common aspect of each of these schemes is the dependence upon a direct, mechanical path for every I/O. This limits achievable density in pin and ball grid arrays and creates rework and compliance problems in very high-density solder bump arrays. The International Semiconductor Technology Roadmap anticipates future high-performance systems requiring 4,000-plus pins and that current technologies cannot scale to the required densities.

We believe ac-coupled interconnects will more than exceed this target while providing a simple mechanical interface. We have researched a novel physical structure, buried solder bumps, that can be used as a solution for providing dc power and ground connections across the same surface as the ac connections. When used in conjunction with receivers that tolerate non-return-to-zero data patterns and current-mode signaling, highly effective interconnects can be built.

The central thesis in the work hinges on the recognition that the dc component of a digital signal carries no information, and that noncontacting ac connections can be built to be a lot denser and simpler than dc connections. An array of noncontacting structures is inherently denser, more compliant and more mechanically robust than an array of contacting structures. By imposing direct contacts only where dc signal transfers are needed allows very high-density interconnects to be realized, and alleviates the compliance and rework problems encountered in other high-density interconnect technologies.

Essentially, the buried solder bump concept allows both dc connections and ac-coupled paths via capacitive or inductive coupling across the same interface, while maintaining low power, high density and high-data-rate communication between integrated circuits. To have numerous dc paths, physical connections must be established, but even the most aggressive connection methodologies introduce a gap between the chip and substrate in the tens of microns. To implement capacitive coupling, however, the chip and substrate must be brought into close proximity (i.e., between 2 and 5 microns apart).

This new physical structure allows both chip-to-chip communication via ac-coupled interconnects and dc paths across the chip-substrate interface. The fabrication process of the physical structure is compatible with standard CMOS processing techniques. As a demonstration, the substrate has been fabricated from a silicon wafer that consists of multiple ICs and a common substrate.

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