Field programmable mixed-signal SoC offer more levels of integration

Recent advances in programmable devices have provided a viable solution for rapid prototyping of complex systems. Time-to-market can be minimized and engineering changes can be made late in the design cycle. The main focus for programmable devices has been on digital circuits like FPGAs, CPLDs and reconfigurable processors. Discrete programmable analog arrays have also been released as products.

For embedded systems, the typical application makes use of a small processor or controller that coordinates the execution and processing of data from peripheral devices. The integration of a microcontroller and programmable analog and digital blocks allows realization of a low-cost, single-chip solution for embedded systems. A configurable mixed-signal microcontroller system offers significant benefits. One device can support a wide range of applications, since programmable resources can be optimized to support a target application without the time and cost of designing a custom ASIC. A high level of silicon efficiency can be achieved by reconfiguring the programmable resources on the fly to implement functionality as needed by the application.

The programmable architecture makes use of dedicated blocks architected for specific functions at a moderate level of abstraction, in contrast to an FPGA or CPLD, both of which use low-level, general-purpose blocks. The microcontroller can be used to add more generic programmability in software. This approach is significantly less expensive in terms of die area, an important objective in the microcontroller market.

The architecture for what we believe to be one of the first mixed-signal field-programmable system-on-a-chip (FPSOC) device integrates a 24-MHz 8-bit microcontroller, flash memory, SRAM, programmable analog and digital blocks, and on-chip clock generation. Programmable interconnect has been designed to allow analog and digital blocks to be combined to form a wide variety of functional modules. The on-chip clocking solution enables the device to function with only a power supply and no other external components. The chip family is fabricated in a 0.45-micron Sonos CMOS technology, offering speeds to 24 MHz at 5 volts (12 MHz at 3.3 V) and flash memory sizes to 16k.

The analog blocks are divided into programmable switched-capacitor (SC) blocks, continuous-time (CT) amplifier blocks and programmable reference generators. The SC and CT blocks are arranged in a 4 x 3 array. Local interconnect is based upon a nearest-neighbor scheme and is programmable to allow communication between blocks to create more complex functions. Common resources on each column include a buffered analog output bus, a comparator bus that interfaces to the digital blocks and a column clock. Each column clock is generated by a two-phase nonoverlapping clock generator with an individually programmable input clock ranging from 32 kHz to 4 MHz.

The digital programmable blocks are organized as a linear array. This allows blocks to be chained together to create higher-precision modules. Two global buses, one for input and one for output, serve to map the connections between I/O pins and digital block I/O. Each digital block has a selection of global buses it can interface to and, in turn, each global bus can drive or be driven by a selection of I/O pins. This provides great flexibility in I/O pin allocation, allowing designers to optimize board layout. Memory-mapped registers in the I/O address space of the microcontroller are used to program specific functions, modes and interconnect configurations of the analog and digital programmable blocks.

These registers may be configured during the boot-up and initialization of the device, or they can be dynamically reconfigured during normal operation. In both cases the configuration process is under firmware control. The definition of the analog microarchitecture is a key feature in the design of a mixed-signal programmable processor. Early efforts provided programming of transistor primitives. Recent efforts at analog arrays have focused on higher levels of abstraction and more complex routing architectures.

The higher level of abstraction improves performance by limiting the choices of circuit topology and optimizing parasitics in the remaining programmable choices. Single-ended circuitry was used to conserve area and simplify the programmable routing.

The analog circuits need to support 8- to 12-bit resolutions. In addition, gain amplifier paths in the range of 50 to 100 need to be supported for sensor applications. The gain requirement means that either large capacitors must be provided for switched-capacitor stages to minimize kT/C noise or some type of continuous-time processing is needed for lower noise amplification. The basic block was defined as an op amp and dedicated resources such as resistors, switches and capacitors.

Two types of blocks were created, one with an op amp and resistors dedicated to continuous-time signal processing and high-gain functions, and the other with an op amp and capacitors for switched-capacitor signal processing. Switches were used in both blocks to multiplex and route local interconnect. Local connections within the block were used to configure basic functions and interblock connections were used to govern how blocks would be connected to create more complex functions.

An "A" type switched-capacitor block is built around a switched-capacitor integrator with three capacitor arrays for the input branches and an adjustable integrating capacitor branch. Functions such as a delta-sigma modulator, gain amplifier, D/A converter or differencing amplifier can be implemented in one block. This block can be combined with the "B" type of SC block to build biquad filters. The basic continuous-time block — a modified version of a previously reported programmable amplifier — can be used for high-gain functions. Two blocks can be combined to form a differential amplifier.

The digital PSOC blocks are designed to offer an array of peripheral functions commonly used in microcontroller applications. The key difference in this architecture is in the configurability and interconnection of these digital resources. A specific set of fixed functions, such as timers, counters, pulse-width modulators, cyclic redundancy checkers, pseudorandom sequencers and dead-band generators, are available in all digital blocks.

A second type of digital block has all these basic functions plus UART and SPI communications capability. There are four configuration registers in each digital block that control the function, mode of operation, inputs and outputs. In this scheme, the granularity of configuration is very coarse.

The digital block is a highly optimized logic block consisting of hardware structures that are common to the required set of functions. By contrast, an FPGA implementation, which has a very fine level of granularity, would provide these and many more potential functions, but at a much higher cost in terms of die area and configuration complexity. The approach in this architecture reflects the target microcontroller market, which is extremely cost-sensitive.

For the basic functional hardware components in a digital block, the data path consists of three data registers (DR0 to DR2) and a fourth register that is used for status and control (DR3). Each register has multiple functions, depending on the configuration programming. Each block has two inputs, data and clock; two function-dependent outputs, and a CPU interrupt. The basic digital PSOC block is 8 bits wide. The nearest-neighbor blocks may be programmatically chained together to create functions of larger data widths.

For example, the eight available digital blocks may be configured as eight 8-bit timers, four 16-bit timers, two 32-bit timers or any arbitrary combination of these and other of the available functions that can be mapped onto the array.

The characterization of an FPSOC device is a formidable challenge. Low-level specifications such as gain and offset of an op amp are difficult to translate to blocks defined by firmware. Performance of the FPSOC device is currently evaluated through the use of functional modules.

A programmable 12-bit incremental A/D can show how modules are constructed on this architecture. The analog component of an incremental A/D can be constructed from one switched-capacitor block. The output of the SC block is digitized and driven onto the analog-to-digital comparator bus interface. To perform the digital portion of the A/D, two digital blocks are allocated. One, configured as a counter, is used to integrate the number of clocks that the output is positive, and the other is configured as a timer which is used to set the overall conversion time, generating an interrupt when the result is ready to read. To achieve a higher level of hardware efficiency, two 8-bit blocks are allocated for all digital functions. The slower processing rate of the upper 4 bits of these functions allows them to be implemented in firmware.

To address the issue of programming complexity, a suite of software tools called PSOC TM Designer was developed. The software uses preconfigured User Modules to facilitate programming. A User Module is a set of information that defines a functional module. In addition, a Device Editor allows users to select various User Modules, instantiate them in the arrays and set many of their parameters. The Device Editor helps users with placement, since functions can map to a number of permutations. Additional C code can be used to integrate the application modules.

A level of system integration not previously possible can be quickly achieved by building applications from basic functional modules through PSOC Designer. End-to-end mixed-signal chains can be implemented that include input buffering and amplification, filtering, A/D or D/A conversion, and DSP using the MAC and microcontroller. Depending upon the resource utilization, multiple channels of these signal chains can be implemented or resources can be dynamically reconfigured as the application requires.

One example of this kind of system integration can be seen in the design of an RF-ID interrogator. When an RF-ID tag is brought into proximity with an antenna circuit a small signal data input is generated in amplitude-shift-key format. The input from the antenna must be conditioned and digitized so that the CPU can interpret the received data. This can be accomplished with a signal chain consisting of a programmable-gain amplifier, a low-pass filter and a programmable threshold comparator. The output of the comparator is driven onto the comparator bus, which can be polled by the CPU as a read-only register.

This implementation takes two continuous-time blocks for the amplifier and comparator and two switched-capacitor blocks for the low-pass filter. One digital block is used to generate a frequency reference for the antenna circuit. Compared with a discrete implementation, it was shown that the integrated solution reduced component count from 47 to two — a 96 percent decrease — and power consumption from 110 to 40 milliwatts, a 64 percent decrease, while demonstrating equivalent or better performance metrics.

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