MOSFET design simplifies DRAM

Details on a compact memory architecture aimed at high-performance, low-cost embedded DRAM for subquarter-micron generations will be presented at the Custom Integrated Circuits Conference this week. The following article contains excerpts from the paper, titled "A Simple 1-T Capacitorless Memory Cell for High-Performance Embedded DRAMs." It is reprinted with permission from the IEEE 2002 CICC.

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By exploiting the floating-body effect of partially depleted silicon-on-insulator devices, a one-transistor memory cell can be integrated in a pure-logic SOI technology without adding any process step. The data retention, device operation principles and reliability make it ideal for high-performance embedded-DRAM applications while reducing the cell area by a factor of two.

The use of embedded DRAMs is accelerating due to the tremendous advantages eDRAM offers in chip functionality, chip size and bandwidth for system-on-chip applications. Logic or standalone DRAM technologies have been used to realize eDRAMs. Logic-based technologies offer the advantages of addressing high-end system design needs and of being compatible with existing standard-cell libraries and cores that can just be plugged in, but suffer from high added cost. A 25 percent cost increase, or five to eight added masking steps, are typical for standard one-transistor, one-capacitor (1T/1C) DRAM cells integrating complex stacked or trench capacitors. In addition, as high-performance logic moves to SOI technology, adding a DRAM array becomes less trivial and process complexity increases further.

Our research team has recently shown that by using a partially depleted (PD) SOI N- or P-MOSFET, a simple capacitorless eDRAM cell can be made without adding a single process step to an SOI CMOS technology. The resulting 1T-DRAM cell has a single transistor, an area two times smaller than regular logic-based eDRAM cells, and performance and reliability characteristics compatible with most eDRAM applications.

To demonstrate the proposed concept, we used MOSFETs made with 0.25-micrometer and advanced 0.13-micron PD SOI CMOS technologies. The devices, provided by LETI (Grenoble, France) and IMEC (Leuven, Belgium), integrate state-of-the-art logic processes on bonded SOI wafers. The top silicon film is 100 nanometers thick. The gate and diffusion regions comprise self-aligned silicide, and a complex multilevel metallization scheme completes the process.

For an N-MOSFET, applying a positive drain voltage pulse creates an excess positive charge in the device body by means of the impact-ionization mechanism. This increases the channel current Ids (state "1"). Positive drain and gate voltage pulses are used to create an excess negative charge in the body by removing the holes. This decreases Ids ("state 0"). A positive or negative charge in the body of PD SOI MOSFETs is therefore used to store the "1" or "0" binary states.

The information is read by comparing the current Ids of the selected cell with the current of a reference cell using a current-mode sense amplifier. The read condition is done at low Vd values so as not to alter the cell and reference-cell states. During a whole refresh interval, reading data does not disturb the stored information, allowing a nondestructive read operation that is not possible in standard 1T/1C DRAMs. Simulations performed with a compact analytical model and with ISE TCAD tools confirm the experimental data.

Our measurements and simulations show that N-channel or P-channel PD SOI devices can be used as 1T-DRAM cells. Standard eDRAM cells built in a logic technology have an area between 18 and 26 F2, where F is the technology minimum feature size.

A denser array arrangement can be achieved with the 1T-DRAM cell by sharing adjacent-cell source and drain regions. With such an arrangement, a 9- to 13-F2 cell area can be laid out for high-density memory applications. This corresponds to a gain of a factor of two in cell area. Each DRAM cell is therefore defined by the intersection of two lines: a word line for gate connections and a bit line for drain connections. All source nodes are connected to source lines that are shorted together on the array edge.

One of the most critical parameters of a new DRAM cell is its data retention. For standalone DRAM applications, retention times of a few hundred milliseconds to a few seconds are targeted at 85 degrees C. For eDRAM applications, more relaxed values are tolerated as a result of the substantially higher bandwidth, and retention times of a few milliseconds are targeted.

If we define the characteristic retention time Tc as the time it takes to close the programming window by 50 percent, the 1T-DRAM cell proposed in this work has Tc values of a few tens of seconds at 25 degrees C and above 1 second at 85 degrees C for large devices made in a 0.25-micron technology. This value drops to 15 to 30 milliseconds at 85 degrees C for small devices integrated with the same technology.

As high-performance logic technologies move to SOI, this approach offers an elegant solution to integrating DRAM arrays on SOI. The cell area is two times smaller than actual eDRAM cells. Data retention, cell disturbance issues and device reliability-characterized on 0.25- and 0.13-micron devices-are compatible with eDRAM requirements. This concept should allow the manufacture of high-performance, low-cost eDRAMs for sub-quarter-micron generations.

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