Dual-band issue: super-heterodyne v.s. zero IF

Dual-band issue: super-heterodyne v.s. zero IF
The success of dual-band WLAN products will be determined predominantly by their cost compared to a single-band product. They may reach critical mass only if consumers are willing to pay the extra cost for them relative to increasingly cheaper 802.11b systems.

A dual-band (DB) chip set for client application can be functionally viewed as a composite of distinct 802.11a and 802.11b chip sets, each with its own radio, modem and media access control subsystems that share a common host interface, for only one path (802.11a or 802.11b) may be active at any time. But in reality, this brute force approach is far too costly to implement and takes up too much real estate on the printed-circuit board to make it feasible for a client form factor. Alternatively, a DB chip set can comprise three main building blocks: a radio subsystem having dual transceiver capabilities for 5-GHz and 2.4-GHz bands, a modem that supports CCK and OFDM modulations and a unified media access controller (MAC) with support for 802.11a, 802.11b and, potentially, 802.11g.

To reduce the cost of such a chip set, the first order of integration is the combination of the OFDM and the CCK modems, the media access control functions and the host interface logic on a CMOS monolithic die. This is achievable since these functions are fundamentally all digital circuitry and, in fact, many WLAN vendors are developing products in this manner. The CCK and OFDM and modems can be designed using dedicated hard-wired DSP engines for each modulation scheme or they can be implemented via an embedded programmable DSP processor, or a combination of the two. The decision on which is the ideal modem implementation is subject to debate based on the tradeoffs of cost, flexibility, performance and power consumption. The 802.11 MAC is best implemented in software running on an on-chip embedded processor for maximum flexibility with some hardware acceleration for the controller.

The decision to use a software MAC has pretty obvious benefits for the flexibility to support the 802.11a, 802.11b and 802.11g protocols as well as the quality-of-service and security standards soon to be ratified by the IEEE standards body. Furthermore, a MAC designed to support 54Mbits/s for 802.11a can easily support the lower data rates of 802.11b and 802.11g. Therefore, since the integration of the CCK modem, OFDM modem and MAC is an obvious path being taken by many chip set vendors and one can clearly see that a nonintegrated approach will result in cost and board real estate penalties, the main area of cost reduction in a DB chip set is the radio architecture.

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The Zero IF (ZIF) radio transceiver is a direct-conversion architecture, meaning that it utilizes one mixer stage to convert the desired signal directly to and from the baseband without any IF stages and without the need for external SAW filters. Most ZIF radio designs also integrate the low noise amplifier, voltage-controlled oscillator (VCO) and the baseband filters on a monolithic die. In fact, such integrated single chip ZIF transceivers have been proved for many years in cellular and pager applications and they are beginning to emerge in WLAN radio designs as well.

Some of the common RF problems inherent with the ZIF architecture are dc offset, flicker noise and LO pulling. Dc offsets are mainly generated by the LO leakage, which self-mixes, thereby creating a dc component in the signal chain that affects the receiver performance and can cause the RF stages to saturate. Flicker noise, also known as 1/f noise, is low-frequency device noise that can corrupt signals in the receiver chain. Flicker noise is more pronounced with the ZIF architecture because of the direct conversion to low-frequency baseband. Another concern with direct conversion is the pulling of the LO by the PA output, which affects the direct upconversion process. This is because the high-power PA output, which has a spectrum centered around the LO frequency, can disturb ("pull") the transmitter VCO.

Recent advances in radio and modem designs are able to resolve these matters through a combination of proprietary radio design techniques and system algorithms in the baseband. For instance, dc offset can be addressed via a compensation scheme in which the offset is measured and reduced via unique radio and baseband algorithm.

In contrast, the superheterodyne (or dual-conversion) transceiver is considered the classic radio architecture in which the received signal is downconverted to baseband frequency in two stages. This two-stage receiver and transmitter architecture uses an RF block to convert an incoming signal to an IF where image suppression and channel selection are performed with a narrow channel-select filter, such as a SAW, or ceramic filters. The now-filtered signal is then further downconverted to the baseband frequency, which is then digitized and demodulated in a DSP. This radio architecture has been used for decades, in part due to its excellent sensitivity and selectivity characteristics. This, however, come at the expense of more complexity and cost, for such radio implementation typically requires an RF chip and an IF chip as well as discrete SAW filters and VCO/synthesizers.

The bill of materials for a dual-conversion radio design is more expensive than for a direct-conversion design for a single-band WLAN network interface card, but the cost discrepancy is increased when the chip set has to handle two bands. A dual-band design using a superheterodyne transceiver needs a 5-Ghz RF stage and a 2.4-GHz RF stage, discreet IF synthesizers/VCO, two SAW filters for image rejection and for channel selection for each band and a common IF block driven by a discreet IF VCO. Assuming that this architecture uses an integrated modem/MAC IC, a dual-band chip set solution will require nine components.

On the other hand, the lowest cost DB approach is to combine the two ZIF transceivers into a single DB radio built on CMOS. This is entirely possible because of the direct conversion of the ZIF transceiver architecture and the integration capability of CMOS process. In fact, the 2.4- and 5-GHz ZIF transceiver circuitry can be laid side by side on a monolithic die without much impact to the die size or package cost. This approach results in a two-chip solution without the need for external components such as SAW filters. In fact, assuming that the dual-conversion chip set and the ZIF chip sets are priced the same, the latter architecture's materials cost at least $7 less, which is very significant in relation to the overall cost-reduction effort of the complete dual-band system design.