Greek EDA startup offers RF design tool

Greek EDA startup offers RF design tool
Santa Cruz, Calif. - Helic SA has launched an inductance-modeling tool that the company says will slash development costs for wireless transceiver designs. VeloceRF supports full-chip extraction of inductance and mutual inductance and automatically synthesizes spiral inductor layouts, according to the Athens, Greece, company.

Founded in 2000, Helic provides the PolyRadio RF intellectual-property (IP) portfolio, which includes transceiver designs for networks such as GSM and wireless LANs. While Helic previously developed a customized inductance-modeling tool called Helmet with Atmel Corp., VeloceRF is its first entry into the commercial EDA market. The tool is available as a module within Cadence Design Systems' Virtuoso platform.

Yorgos Koutsoyannapoulos, Helic's CEO, called VeloceRF a "novel EDA tool" aimed at full-chip RF modeling, RF IP portability and reuse. The goal, he said, is "to elevate RF IC and systems-in-package design from an exotic art to a systematic design process." He said the tool can cut development costs by more than 50 percent and result in die-size savings of more than 35 percent for complex RF transceivers.

VeloceRF, he said, "makes it possible to design and capture IP blocks that can be subsequently adapted and retargeted for a variety of silicon processes, frequency bands and standards. On top of this, using Helic's tools, the end user of the IP can reconfigure it to generate customized silicon instances. This has not been possible in the past."

VeloceRF is an electromagnetic-modeling tool that extracts RLCK (resistance-inductance-capacitance-mutual inductance) netlists for spiral inductors, transformers, arbitrarily shaped inductive elements and RF interconnect lines. An automated layout synthesis feature, Spiral Wizard, generates constraint-driven layouts for spiral-inductor devices or multi-inductor structures.

VeloceRF works with existing commercial RC extraction tools. "VeloceRF, in a nutshell, specializes in parasitic and intentional inductances, which are either not supported or too cumbersome to extract with state-of-the-art extractor tools," said Helic co-founder Sotiris Bantas, the vice president of technology.

The offering can be used at different stages in the design cycle. During schematic capture, it can extract models and optimize the circuit, taking into account the nonideal performance of inductive elements. During layout, it can help with floor planning and the placement of inductive structures. After layout, it interfaces with RC extraction tools and physical-verification tools.

The input to VeloceRF during the prelayout phase is inductive-structure specifications, using either Spiral Wizard or direct generation of models. The output is spiral-structure geometries and, during the layout phase, a full-layout database and a Spice-compatible netlist.

Helic says the tool is extremely fast, with an ability to run extraction on a cell with 12 spiral inductors in 40 seconds. Bantas said that accuracy has been proven with real silicon examples. One concern about RLCK extraction is the potential to overwhelm Spice simulators, but that has not been a problem, he said. "Experience in typical RF IC blocks shows that lumped-element models generated by VeloceRF do not overwhelm simulators even in very complex cases," said Bantas. "Simulation times for complex RF circuits are slightly increased, no more than 15 to 20 percent."

Spiral Wizard directly supports Cadence's Virtuoso layout platform, but has a separate executable that can plug into other platforms as well, Bantas said.

Bantas said the tool has been tested for foundries including Atmel, Jazz Semiconductors, Agere and Taiwan Semiconductor Manufacturing, in processes including silicon germanium, bipolar and CMOS.

VeloceRF is available as a Virtuoso module starting at $19,000 for a one-year lease. Helic has a North American sales office in Los Gatos, Calif.

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