EDA users call for better power, timing tools

EDA users call for better power, timing tools
SAN JOSE, Calif. — Better timing and power tools are critically needed for ASIC and processor design, according to chip designers on a Sunday evening (Nov. 9) panel at the International Conference on Computer-Aided Design (ICCAD) here. Panelists also shared their views on what they'd provide if they were starting an EDA company.

Moderated by Leon Stok, senior manager for design automation at IBM's T.J. Watson Research Center, the interactive panel was entitled "CAD for high-end design: help, hope or hype?" Stok asked panelists what they'd buy if their EDA budgets were increased by 40 percent. He then invited audience members to make pitches to the panelists, who voted on the best idea.

Stefan Rusu, senior principal engineer at Intel's enterprise processor division, said he'd focus on tools for timing, power, and noise. He said that power and leakage reduction should be part of all CAD tools and flows, and he called for enhanced noise analysis and avoidance, improved timing models, more accurate parasitic extraction, and statistical modeling of on-die process variations.

"The bottom line is that we have to look at simultaneous optimization of timing, power, and noise," Rusu said. He also suggested moving all design flows to Intel architecture machines running Linux, to get better performance and lower cost of ownership.

Peter Hofstee, senior technical staff member for IBM's emerging products microelectronics division, said he'd invest in power-related tools, including ac power verification, dc power estimation and analysis, and power-optimal clock distribution. He also said he'd like tools that can analyze the effects of IR drop, temperature, and process variations on timing.

Richard Paul, technical lead for ASIC development at Cisco Systems, made a pitch for better power rail implementation and analysis. "It doesn't seem that anyone provides a solution that fits with all the ASIC vendors' complicated requirements," he said. "Every time we make a floorplan modification, we don't get the netlist for weeks while vendors do power rail implementation."

"I want power analysis that works," said Jeff Dauber, director of VLSI hardware engineering at Apple Computer. "Our power numbers are fundamentally wrong because the numbers we feed into these tools are invented. I'm desperate for just about anything in this area."

Dauber also said he'd like an engineering change order (ECO) tool that allows rapid modifications to chip layouts, and an analog/digital simulation tool that runs quickly and can handle several hundred clock domains.

An FPGA designer's perspective came from Richard Vallee, vice president of sales and marketing at Canadian design house Amirix Systems Inc. He said he wanted faster simulation and verification time and faster optimization time. But he also said he expected FPGA vendor tools to be "free or almost free," and third-party tools to be "low cost."

Audience members were then given a minute and a half each to make a pitch to the panelists. Suggestions included probabilistic timing and power analysis, making all EDA tools open-source, an automated system-level compiler, an ECO tool that could change design specifications automatically, self-timed designs, de-skewed circuits, and more support for university research. Panelists selected open source as the top vote-getter, followed by the ECO tool.

Stok's second question asked panelists what kind of EDA company they'd start, or want to work for, if they took a job in that sector. Hoftsee's answer was "wire-driven" synthesis that focuses on interconnects first. Paul said he'd develop a database translator to bridge the gap between proprietary databases and divergent file formats.

Rusu said he'd develop an integrated suite including synthesis, floorplanning, and simultaneous noise, verification, and power optimization. His second idea was a high-level modeling suite allowing "what if" architectural exploration. Joe Hanson, director of marketing for system-level development tools at Altera, said he'd want to develop a system-level compiler that could generate correct-by-construction logic.

Audience members voted on these suggestions, and Hofstee's "wires first" synthesis won the show of hands.

Stok's final question, asked in the last few minutes of the panel, was the hardest. Panelists were asked which tools they'd cut if their EDA budgets were slashed by 40 percent.

"Tools that try to solve complex problems fall short," said Hofstee. "If I have to cut, in general, synthesis tools go away in favor of analysis tools." Paul, on the other hand, said he'd cut floorplanning. "They've put in so many features that floorplanners are getting complicated to use," he said.

ICCAD is at the Doubletree Hotel in San Jose, Calif., through November 13.