Verilog schism looms as Accellera misses deadline

Verilog schism looms as Accellera misses deadline
SANTA CRUZ, Calif. — With the failure of the Accellera standards organization to meet an August IEEE deadline for the donation of SystemVerilog technology, two separate and possibly incompatible versions of Verilog appear to be emerging.

As a result, chip designers may have to choose between Accellera's SystemVerilog, heavily backed by Synopsys, and the forthcoming IEEE 1364-2005 Verilog, backed by Cadence Design Systems and Verisity.

The IEEE 1364 Working Group, also known as the Verilog Standards Group (VSG), announced Thursday (Sept. 4) that it has received nine technology donations from Cadence, Verisity, Fintronic and Jeda Technologies. These will be considered for inclusion in IEEE 1364-2005 Verilog. The VSG is also announcing that the open period for technology donations is now closed.

"I'm also on the board of Accellera, and there were three motions to try to get Accellera to work with the IEEE to make one Verilog," said Mike McNamara, VSG chair. "For whatever reason, that's not happening."

McNamara said Accellera has decided not to donate anything until March 2004, in which case, he said, SystemVerilog will probably have to wait until the next IEEE revision in 2009 or 2010. Meanwhile, the VSG has accepted technology donations that appear to overlap with many of the features in SystemVerilog.

Dennis Brophy, Accellera chairman, said his organization has not set a date for donating SystemVerilog to the IEEE, but added that it isn't ready yet. "Our plan is to get to a point of stability," he said. "We want to end up with proven technology and end up with something solid. It would be premature to give an exact date."

"If they [IEEE] want to duplicate SystemVerilog, fine, but they're years behind where SystemVerilog is today," Brophy said. "They are on the path to duplicating work that may be unnecessary."

McNamara said the new technology donations cover much of the same ground as SystemVerilog. For example, Verisity has donated verification constructs from its "e" language, while SystemVerilog takes verification constructs from Synopsys' competing Vera language. While SystemVerilog provides assertion support, there's a proposal to link IEEE 1364-2005 with the Accellera Property Specification Language.

The Cadence donations include text-based IP encryption, Verilog extension mechanisms, data type definitions, system task-based constraints and randomization as well as Verilog procedural interface extensions. Fintronic has donated its Verilog separate compilation technology. Startup Jeda Technologies is offering technology from its Jeda-X verification and modeling platform.

The new donations will be described at the IEEE 1364 web site Sept. 4.

With these donations, McNamara said, the VSG will "get to work" and come up with a final draft by December 2004. This will be followed by a six-month balloting cycle, with the new standard available in mid 2005.

Brophy noted that most EDA vendors don't even fully implement the older IEEE Verilog 2001 standard yet. "It will be sometime between 2005 and 2008 before people can get hold of it [1364-2005] and start implementing. SystemVerilog is available today for that purpose."

"I think there's some willingness to make one version of Verilog, but it doesn't seem that all parties are agreeing to that," said McNamara. "It seems like there's a disagreement, a desire to control things that's unfortunate."