Designing for process variation at 130 nm

Designing for process variation at 130 nm

Advanced process technologies are generating significant challenges for modern IC designers as the physics of the 130- and 90-nanometer generation bring what were previously noise-level effects to the forefront.

The most common examples include reliability effects such as signal electromigration, power electromigration and IR drop, crosstalk glitch and crosstalk delay. Less well-understood is managing the process variation inherent in process technologies with feature dimensions measured in molecules.

The problem
The proactive management of process variation during the ASIC design process is critical to ensure effective device yields and to keep manufacturing costs down. This requires the calculation and application of margins that account for the customer's required operating frequency across multiple timing corners (voltage, temperature and process) and in all device modes (mission and scan, for example).

During the last few technology generations, second- and third-order physics effects have become first-order. Some of these effects (signal electromigration, crosstalk glitch and others) have progressed through the typical EDA life cycle of:

- Detection-being able to find a problem,

- Correction-being able to fix a problem,

- Prevention-being able to stop a problem from happening.

However, at the 90- and 65-nm nodes, new effects are appearing. Since these effects are understood and quantifiable, they have been added to the design process in the most applicable fashion (whether that be library characterization, cell design, EDA tool changes or increased margins). These include:

- Random dopant fluctuation, which causes on-die Vt variation,

- Idrive variation due to stress effects (STI, edge stress and contact location),

- Leakage variation due to transistor length variation,

- Intradie and intrawafer transistor and thermal variation,

- Known EDA tool inaccuracies.

Some effects can no longer be ignored because they are significant enough to reduce device performance and therefore result in a speed yield loss. This is especially true for items that impact interconnect, which can account for a significant portion of circuit delay.

The solution
At TI we divide and conquer the problem to enable different solutions targeted for each problem. Specifically, we:

- Differentiate design-specific effects from the library and process,

- Differentiate cell-specific effects from design-specific effects,

- Differentiate library from the process.

When possible, the library cells are characterized to include the variation effects that are process- or cell-specific. For analog cells such as sense amps, PLLs and I/Os, that means statistical simulation of usage scenarios. For digital cells, that means characterization with accurate Spice models to take into account variation effects like negative bias process instability, or NBTI.

At the design level we have developed tools that gather design-specific information (including which cell library and silicon process) and calculate the amount of setup-and-hold margin required to meet the customer's requirements, given statistical analysis of variation. This is calculated and reviewed at multiple stages in the design process to ensure that all aspects of the design are evaluated using the most recent implementation results.

In terms of design-specific effects, we look at the entire system surrounding the ASIC. Since the operating environment (temperature and especially voltage) are critical to meeting performance goals, we look at the board power supply variation, the board IR drop, in addition to the worst-case device IR drop and PLL jitter. That allows us to account for any potential reduction in supply voltage.

Design flow implementation
The only thing more important than the calculation of the device-specific margin is how it can be effectively used in physical design. This includes detection, correction and prevention techniques.

The key aspect of the design implementation is to ensure that the device frequency used in implementation includes the necessary amount of margin and that setup-and-hold windows allow for the worst-case variation calculated.

For detection, we use a popular static-timing analysis (STA) tool and its on-chip variation capability. This allows the designer to simulate what would happen if the device performance were to shift by a given percentage and whether the setup-and-hold constraints on flip-flops would still be met. This is typically done late in the design cycle, since the entire physical implementation must be defined to allow for accurate variation analysis.

For correction, the previous approach was to process the STA results, generate an engineering change order (ECO) file to make the necessary circuit adjustments and then run STA again as a final check. While effective, this was a time-consuming find-fix-repeat process that led to schedule unpredictability and was not in line with our 60-day gate-to-tapeout design-cycle time requirements.

The goal of design flow implementation has always been to make designing for variation a natural part of the overall design effort with minimum additional cost in design cycle time or schedule predictability. For that reason, prevention has always been key.

To accomplish that objective, we worked closely with Magma Design Automation to implement a prevention capability that uses the desired amount of design margin during the physical synthesis implementation process. Because Magma does delay calculation, automatic clock tree insertion and expansion, full detailed routing and extraction, it is uniquely able to create an implementation that includes the margin required.

Because it is correct-by-construction, this largely eliminates the time-consuming ECO cycles and helps meet our design cycle time goals.

The result
Because this is one of the newer challenges of designing high-performance systems-on-chip, the implementation over the last few years has concentrated on design team education about the realities of designing with advanced process technologies. The results we've seen have been impressive for our customers as they see their silicon achieve first-pass success.

In all application areas as diverse as high throughput data processing applications for the Internet infrastructure market (6 million to 10 million gates, 300+ MHz, 1,000+ I/Os, flip chip), low power applications for wireless handheld devices and high-performance DSPs, there is nothing that gives a design manager more confidence-and relief-than when his device works the first time he plugs it in.

Tom Vandenberge is the ASIC design system strategy and deployment manager at Texas Instruments Inc.

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