Aptix rolls out transaction-level emulation

Aptix rolls out transaction-level emulation
SANTA CRUZ, Calif. — Bringing transaction-level verification to coemulation, Aptix Corp. this week (Sept. 16) is announcing the Aptix SoC Validation Lab, which includes verification intellectual property from design services firm Zaiq Technologies. The system is touted as providing the first independent implementation of Accellera's Standard Co-Emulation Modeling Interface (SCE-MI).

Aptix' System Explorer hardware platform offers rapid prototyping, but until now it has run with cycle-based or event-driven verification. Transaction-level verification allows engineers to work at a much higher level of abstraction, firing off complicated transactions without worrying about lower-level bus protocols.

"The key here is speed improvement," said Charlie Miller, Aptix senior vice president of marketing. "By adding transactions, a smaller amount of data goes across the interface, and you get a big jump in performance." Compared to cycle or event-based co-emulation, he said, transaction-based coemulation could be 1,000 times faster.

Further, test development can be greatly eased. "Cycle-based verification can be very accurate, but it's very tedious to write an accurate testbench," said Richard Newell, Aptix director of hardware product marketing. "With transactions, a lot of work is carried by the verification IP, or transactor, itself. The test writer can just send a packet, with the lower-level detail handled by the transactor."

Key to the SoC Validation Lab are the "transactors" provided from Zaiq's SystemWare libraries. These provide verification IP for such protocols as Ethernet, SPI, PCI, PCI-X, Packet over Sonet, USB and Amba. A transactor has two portions: a synthesizable bus-functional model, and a C language function that provides an applications programming interface for the test writer.

The transaction-level testbench, at present, must be constructed in C/C++ or SystemC, although Miller said Aptix could support SystemVerilog, Vera, or other hardware verification languages in the future. He noted that Aptix has already announced plans to support Verisity's "e" language.

The test writer works purely at the transaction level. Aptix plans to support a mix of transactions and events in the future, Miller said.

In addition to the transactors, Zaiq has provided its Pre-configured Reusable Environment and testing Platform, which helps users create and organize transaction-level tests. Also included is Zaiq's TestBench Plus transport layer, which communicates test information between C and VHDL or Verilog. It supports threads so that concurrent tasks can be initiated.

Users can write their own transactors if needed. If they're written to support SCE-MI, Newell noted, they should work with emulation products from other vendors as well.

For current Aptix customers, the SoC Validation Lab starts at $75,000 for a one-year license. This price includes Zaiq libraries and software, as well as the SCE-MI interface.