Startup preps FPGA hard/soft co-development tool

San Jose, Calif. - Impulse Inc., a six-person startup in Kirkland, Wash., wants to bring affordable hardware/software co-development to engineers using FPGAs to implement their designs.

President and chief technology officer David Pellerin and chief executive officer Brian Durwood said they want to make it easier and more affordable for software designers as well as hardware designers to do hardware/software co-development of FPGAs containing processor cores.

The company is putting together a development environment, called CoDeveloper, built largely from the open-source Streams-C compiler technology licensed from Los Alamos National Laboratory (see www.eedesign.com/story/OEG20021018S0060), from technology gained from the Stanford University Intermediate Format project, and from shareware and other sources.

Pellerin, a founder of simulation startup Accolade Design Automation, has written four books on VHDL and FPGAs. Durwood, a former vice president of marketing and sales at the Maxtek subsidiary of Tektronix Inc., worked with Pellerin at FPGA router company Data I/O Corp.

"C-to-RTL compilation is an important part of the environment but it is not what we consider the core of the solution," said Pellerin. "Our approach is more that the programmer is given the tools necessary to partition a large design and to take processes and convert some of those to hardware and others of those to traditional processors."

Unlike other providers of hardware/software co-development tools, Impulse focuses only on users targeting FPGA applications, Pellerin said.

The company's price points will reflect the focus on FPGA and software designers, who are accustomed to paying less for tools than ASIC designers, said Pellerin.

"CoDeveloper is intended for embedded designers and systems designers, allowing them to compile ANSI-C language into programmable platforms-one or more FPGAs with one or more processors," said Durwood. "It provides a programming model and a set of tools that allow embedded-system designers and system programs to use their existing tools, IDE [integrated development environment] compilers and debuggers to develop software using standard C, our Impulse C libraries, and generate hardware in the form of HDLs and libraries for software."

VHDL simulator

Impulse is still months away from releasing CoDeveloper to the mass market and did not give further details of its co-development technology. But the company has released a part of the environment and is licensing a combination VHDL simulator/coverage analysis tool called CoValidator, which Impulse licensed from an undisclosed vendor. Impulse licenses the tool for about $895.

"It's a full IEEE 1076-compliant VHDL simulator, plus it has code coverage," said Pellerin.

The coverage engine in CoValidator can identify specific lines of code that are not adequately covered by their HDL test suites or segments of their applications that may be candidates for further testing, optimization or elimination.

CoValidator red-flags sections of source code that have not been executed, identifies branch conditions that that have not been tested and provides detailed coverage reports (in a variety of formats, including HTML) for creating management reports and tracking the progress of test-suite development. Pellerin said CoValidator can be used as a standalone tool for VHDL simulation and coverage analysis or can complement a company's existing EDA tool flow, providing immediate access to advanced VHDL simulation at a lower per-seat cost.

CoValidator is compatible with other, higher-cost VHDL simulators and with widely used FPGA synthesis tools, Impulse said. CoValidator's price will make it possible for customers to add several design seats at a cost typically required for one, the company said, making VHDL simulation available to all engineers on a project and reducing project delays.