A new vision of silicon compilation

A recent article by the Fabless Semiconductor Association (FSA) offers some staggering figures. Average R&D costs for creating a new design have increased to an average of $20 million, while the time it takes to create a new IC design has remained relatively constant since 1995 — 18 to 24 months. This problem is exacerbated by the fact that R&D accounts for only 5% of the total costs related to a particular device.

Additional expenses include 50% for Cost of Sales (COS), 25% for Sales, General, and Administrative (SGA) costs, and 20% for Operating Income (OI) costs. This means that producing a $20 million IC actually requires the existence or creation of a $400 million company. In turn, even assuming a dominant 30% market share, this requires a $1.3 billion market for the device.

Venture firms are increasingly reluctant to invest in new startup chip companies, impacting the ability of companies to innovate. What is required is some way to dramatically reduce the R&D costs associated with a new device, because this has a ripple-on effect with regard to the total costs. For example, reducing the R&D costs for a device from $20 to $10 million would reduce the total costs associated with that device from $400 to $200 million.

One solution is silicon compilation — a tool or tool suite with the ability to take the RTL describing a design, and to automatically generate the corresponding GDSII files used to produce the photomasks. These are used to create the IC. This means that the silicon compiler has to assume control of all of the physical implementation portions of the design process, including synthesis and place-and-route, along with the corresponding power, timing, and signal integrity (SI) analysis engines.

If such a tool could be realized, it would dramatically reduce both the costs and the time-to-market associated with new IC designs.

The concept of silicon compilation originated during the early 1980s with three visionary companies: Seattle Silicon, Silicon Compilers, and Silicon Design Labs. At that time, it was apparent that chips were becoming too complex to be designed at the transistor level, but instead needed to be designed at a higher level of abstraction.

The idea behind the silicon compilers of that era was that chips would be specified as a series of parameterized building blocks. In the same way that a software compiler accepts source code and generates a single binary executable image, so the silicon compiler would take its parameterized blocks, stitch them together, and generate the photomasks required to build transistors and metallization layers.

The original concepts were good on paper, but they were by no means push-button solutions, and each of the implementations contained serious flaws. Eventually, the onset of logic synthesis technology combined with industry-standard HDLs (VHDL and Verilog) removed any economic imperative for the early silicon compilers, and the entire concept fell into disuse.

Today's silicon compilation is similar in concept to the original, in that it accepts a high-level representation of the design and compiles it down to GDSII. Instead of parameterized building blocks, however, the input to the silicon compiler is the captured and verified RTL representation of the design. The silicon compiler then uses existing implementation engines (synthesis, place-and-route) and analysis engines (power, timing, SI) to automatically generate the final GDSII.

Magma is closer than other EDA suppliers, but we don't have a true silicon compiler solution today. We need to get there to make the EDA recovery a reality, and I intend to direct our technical resources toward achieving that goal.

Rajeev Madhavan is chairman and CEO of Magma Design Automation.