Mixed-signal IC layout tools support 'touch and feel'

Mixed-signal IC layout tools support 'touch and feel'
SAN FRANCISCO — Mentor Graphics Corp. is announcing this week a series of IC layout tools intended to complete the design flow for mixed-signal SoCs. Called ICassemble, the tool is designed to complement top-down, hierarchical mixed-signal design with a tool that provides interactive floorplanning and routing.

Using Mentor's IC Station full custom layout environment, the ICassemble tool provides top-down floorplanning, both interactive and fully automatic routing for quasi-analog blocks along with stitching for those blocks with the SoC host.

ICassemble will automate the IC layout process, said Avi Gupta, director of marketing for Mentor's Custom IC Design. Bottlenecks in mixed-signal design caused by layout systems have increased demand for hand layout. At the same time otally automated systems cannot respond to analog contingencies, Gupta said.

A paper published Mentor Graphics (based in Wilsonville, Ore.) estimates that 75 percent of all SoC designs will contain some analog blocks by 2006. End-user applications for these SoCs include video cell phones, MP3 music devices, wireless web browsers and PDAs.

"This demand for increasingly diverse capabilities on a single device, combined with the drive for longer battery life, lower power consumption and smaller sizes, has driven the development of mixed-signal devices on a single chip," the paper said.

Gupta admitted that massive digital ASICs were not necessarily the best substrates for analog cell blocks. He added that Mentor tools were already aiding customers in the automotive electronics business. It's a "Big A, little D capability," he acknowledged.

ICassemble targets Mentor's IC Station tool. With a common database and user interface, SoC designers can plan, implement and connect blocks within a physical layout environment. The tool will significantly reduce the time required to stitch together analog and digital blocks on large chips, Gupta said.

The floorplanner within the tool can be driven by schematics or netlists. They, in turn, "talk" to IRoute, an auto-interactive router, and to ARoute, an automatic, gridless shape-based router. All three components work with user-specified design constraints such as timing, signal integrity, pin placement, wiring and shielding. Built-in design rules automatically adjust the layout to accommodate these priorities.

The floorplanner also allows designers to partition the chip, estimate block sizes and place the blocks while assigning pin locations in order to minimize congestion and the wire lengths of critical signals.

In the early planning stage, IRoute can rapidly route power buses and critical signals to meet timing constraints. It will automatically adhere to constraints on shielding, spacing, wire widths and directions. It also includes a built-in "push and shove" feature — ensuring clearance for critical nets. "That'll save you 25 to 50 keystrokes," Gupta said.

Aroute, meanwhile, provides an iterative rip-up and re-try tool that allows bulk routing of nets, selected by region or group, to rapidly complete chip assembly. "It's a 10x time-saver," Gupta said.

The ICassemble tool is priced at $75,000 and is available now for Linux, Sun Solaris and HP-UX platforms.