Verilog reaches a critical crossroads

Verilog reaches a critical crossroads
Today's EDA community and its customers actively use many languages — including Verilog, VHDL, SystemC, SPICE, e, Vera, PSL/Sugar and C/C++ — for many purposes. Of these, IEEE Verilog 1364 has been the bedrock serving the digital design and verification communities well for nearly 20 years as the unified basis for most of the simulation, verification, and physical implementation. As we approach Verilog's third decade, there is a distinct possibility it could splinter into more than one language. This could spell disaster for all involved.

When designs were smaller and testbenches less complex, Verilog could be used to describe the entire design and testbench. Now a single block is larger and more complex than the entire chip being designed a few years ago. New verification methods have been adopted at the system level, but block level verification remains heavily Verilog-based. Unfortunately, Verilog has not kept up with rapid changes in verification techniques such as abstract data structures, directed random testing, and assertion-based verification.

Extending Verilog for these purposes makes a lot of sense, and would allow design engineers to use a single language and tool set. The engineering community, including Cadence, believes that IEEE Verilog 1364 should be extended on four main fronts:

• Data structures, to raise the level of abstraction in models and testbenches.
• Transaction-based verification capabilities, including directed random testing.
• Assertion-based verification features, supporting both simulation and formal verification.
• An IP encryption format, utilizing industry-standard open encryption algorithms.

A lot of good work has been done within Accellera, a group formed in the year 2000 through unification of Open Verilog International and VHDL International. Accellera's current proposal, SystemVerilog, is based on a combination of various other languages, including: Superlog, acquired by Synopsys with the CoDesign acquisition; ForSpec, an assertion language proposed by Intel; and Vera, also acquired by Synopsys from Systems Science. While the name "SystemVerilog" seems to imply extensions to support system-level design, in fact many of the language constructs added support testbench generation and assertion checking.

Yet there is currently no discussion about how to integrate SystemVerilog with the existing IEEE 1364 standard, as was done with Verilog 2001. In fact, many of the proposed enhancements are in direct conflict with the IEEE standard Verilog and/or reintroduce language features previously rejected by the IEEE 1364 committee.

Cadence believes the EDA community must prevent the existence of two separate Verilog languages. If customers were to adopt SystemVerilog and later discover it is not compatible with other tools, it could create havoc in the design community. This is because SystemVerilog inevitably would be incompatible with the eventual IEEE standard. The issues between SystemVerilog and IEEE 1364 must be resolved before SystemVerilog is standardized. The proper place to get this done is with the IEEE 1364 committee, which owns the Verilog standard.

Mitch Weaver is vice president of marketing for systems verification at Cadence Design Systems, Inc.