Synopsys executive predicts end of VHDL

Synopsys executive predicts end of VHDL
SAN JOSE, Calif. — Synopsys' chairman and chief executive officer Aart de Geus predicted that VHDL will go away in 10 years. De Geus made his prediction at the Synopsys Developers Forum here.

"I think VHDL will be around for a long time — probably for another decade," said DeGeus in a keynote. "At the same time I think SystemVerilog adoption will grow very fast and that is driven by technology. Our position is that we must and want to support VHDL as the industry goes through the transition to widely adopt SystemVerilog. But I don't want to be wishy-washy about the fact that we think SystemVerilog overtime will replace it."

De Geus said that he believes many of the unique features found in VHDL will in time find their way into SystemVerilog. "We will support VHDL users through the transition to System Verilog," he said.

At DVCon last month, de Geus gave a keynote promoting the SystemVerilog language as the next evolution of Verilog and how Verilog will bloom into SystemVerilog with the addition of assertions. Then, the keynote omitted de Geus' views on the fate of VHDL, which until recent years has been the arch-rival of the Verilog language.

De Geus' views on the fate of VHDL were noted by ESNUG and Deepchip.com moderator John Cooley, who wrote about this in his recent column titled "VHDL, the new Latin".

De Geus said that he expects Vera testbench language will also go away eventually as SystemVerilog adopts Vera constructs.

A year ago Synopsys donated many constructs of Vera to standards body Accellera, which is overseeing the standardization SystemVerilog.

De Geus said that he believes SystemC, once backed by Synopsys over SystemVerilog as the next-generation design language before Synopsys bought SystemVerilog's original creator CoDesign, will likely become the next evolution of design languages after SystemVerilog becomes established.

Accellera Chairman Dennis Brophy said he doesn't think de Geus is crazy and that "SystemVerilog will become the foundation upon which SystemC will eventually grow."