News & Analysis
SystemVerilog won't cause incompatible standards
Stu Sutherland
4/11/2003 2:02 PM EDT
In an EDA Views column posted to EEdesign April 4, 2003, Mitch Weaver of Cadence Design Systems wrote of the need to extend the Verilog standard to support ever-increasing design sizes. Mr. Weaver then expressed concern that the SystemVerilog standard being developed by Accellera does not properly address the needs of extending the IEEE Verilog standard.
For those not familiar with what SystemVerilog is, let me give a short definition. SystemVerilog is a set of extensions to the IEEE 1364-2001 Verilog standard. These extensions significantly expand the capabilities of Verilog for modeling and verifying extremely large, complex digital designs.
I would like to point out some misconceptions in Mr. Weaver's article. Mr. Weaver stated, "Yet there is currently no discussion about how to integrate SystemVerilog with the existing IEEE 1364 standard, as was done with Verilog 2001. In fact, many of the proposed enhancements are in direct conflict with the IEEE standard Verilog and/or reintroduce language features previously rejected by the IEEE 1364 committee."
I feel Mr. Weaver's claims are in error. There is a working relationship between Accellera and the IEEE 1364 Verilog Standards Group (VSG). The IEEE 1364 standards group is well aware of, and has considerable influence on, the development of Accellera's SystemVerilog extensions to the Verilog language. I have been a member of the IEEE 1364 Verilog Standards Group since its inception in 1993, and am currently serving as the chair of the PLI task force within the 1364 VSG. I have been a member of the Accellera SystemVerilog standards committee since its inception in 2000, and serve as the editor of the SystemVerilog Language Reference Manual.
Other Verilog experts, such as Cliff Cummings of Sunburst Design and Stefen Boyd of Boyd Technology, also serve on both the IEEE and SystemVerilog standards groups. Phil Moorby, the creator of the Verilog language and keenly aware of the long history and evolution of Verilog, is a prominent member of the SystemVerilog standards committee. Several major EDA vendors who implement IEEE compliant Verilog simulators, synthesis compilers, and other Verilog tools have technical experts on both the IEEE 1364 and SystemVerilog committees. There is a great deal of synergy between the IEEE 1364 Verilog standard and the Accellera SystemVerilog standard.
Full compatibility with the IEEE Verilog standard is a prime consideration for each and every feature that has been added to the Verilog HDL under the moniker of "SystemVerilog." The SystemVerilog standards committee has sent great ideas back to the drawing board, sometimes multiple times, until that idea could be implemented syntactically and semantically in a manner that would be compatible with the current IEEE 1364-2001 Verilog standard. It is worth noting that Accellera financially sponsors much of the cost for the IEEE 1364 Verilog standard development, as well as several electronic design related standards.
Full compatibility
It is fully to Accellera's advantage to ensure that SystemVerilog is 100 percent compatible with the IEEE Verilog standard. Mr. Weaver's statement that "many of the proposed enhancements are in direct conflict with the IEEE standard Verilog" is not correct.
Mr. Weaver stated that SystemVerilog has reintroduced "language features previously rejected by the IEEE 1364 committee." This is putting a misleading marketing spin on the true facts. On the IEEE VSG, we considered hundreds of enhancements for Verilog as we developed the Verilog-2001 standard. Many worthy enhancements were rejected at that time simply because there was either not enough time to fully specify the enhancement, or because we felt it might add too much to Verilog-2001, thereby making it too difficult for EDA vendors to remain IEEE 1364 compliant.
Rejecting a feature for consideration in the Verilog-2001 standard, however, in no way implied that the feature was not desirable or might not be considered for a future version of Verilog standard. For example, the plus-plus (++) operator from C is one of the features that was considered for Verilog-2001 and rejected. It was rejected because a prominent EDA company voiced concerns regarding synthesis of the operator, and there was not adequate time for the IEEE 1364 committee to resolve those concerns.
The Accellera SystemVerilog enhancements to Verilog include the ++ operator. Accellera has invested the time to fully define the semantics of the operator, and that EDA company is satisfied that its concerns have been resolved. Two other examples of desirable enhancements rejected for Verilog-2001 are enumerated types and record data types. These were rejected for inclusion in the Verilog-2001 standard because there was not enough time to fully specify the enhancements. Those of us that are representing the IEEE 1364 standards group on the Accellera SystemVerilog standards committee are excited that these enhancements have now been specified and added to SystemVerilog.
It is important to note that Accellera is not inventing SystemVerilog enhancements from thin air. Accellera has based the SystemVerilog enhancements to Verilog-2001 on proven technologies that have already been implemented in commercial software tools. A number of companies — Co-design, Verisity, IBM, Cadence and Synopsys to mention just a few — have donated proven and established technologies to Accellera. The Accellera SystemVerilog standard unifies those technologies with their varied syntax and semantics into a single, common language that is based on a Verilog-style syntax and semantics.
Enhancements such as the ++ operator, enumerated types, and structures were unproven proposals in the 1990's when the Verilog-2001 standard was being defined. Proprietary languages such as Vera and Superlog have subsequently proven that these constructs can be implemented in Verilog simulation environments. The donation of these languages to Accellera has made it possible to define the enhancements to the Verilog-2001 standard with a high degree of confidence that the semantics are correct and are compatible with the Verilog standard.
Mr. Weaver stated in his article, "Cadence believes the EDA community must prevent the existence of two separate Verilog languages. If customers were to adopt SystemVerilog and later discover it is not compatible with other tools, it could create havoc in the design community. This is because SystemVerilog inevitably would be incompatible with the eventual IEEE standard. The issues between SystemVerilog and IEEE 1364 must be resolved before SystemVerilog is standardized."
This opinion seems to indicate a misunderstanding of exactly what SystemVerilog is. SystemVerilog is not an independent language that competes with Verilog. SystemVerilog is a set of extensions to the existing IEEE 1364-2001 Verilog standard. Accellera has stated since the very beginning of the development of SystemVerilog that the ultimate goal is for these extensions to be turned over to the IEEE for integration into a future version of the IEEE 1364 Verilog standard. In his article, Mr. Weaver does an admirable job of succinctly stating the need to extend Verilog. He correctly points out that the ever-increasing size of our design and verification tasks has vastly out paced the growth of current HDL standards. SystemVerilog is the evolution of the Verilog standard that Mr. Weaver correctly says is needed.
I would like to acknowledge that Cadence has very technically knowledgeable engineers participating in the development of SystemVerilog, who have made significant contributions to SystemVerilog. The participation and contribution Cadence has made to the SystemVerilog standard is an indication to me that Cadence does understand the significance of the SystemVerilog enhancements to the current IEEE Verilog standard. I am both hopeful and confident that Cadence does intend to provide their customers with the important solutions to design and verification challenges that SystemVerilog offers.
On-line references
Editor's Note: A recent EE Times article more fully explains Cadence's concerns and provides Accellera's response.
Stuart Sutherland is president of Sutherland HDL, a Verilog and SystemVerilog training and consulting company founded in 1992.
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