Statistical analysis to yield better chips

Statistical analysis to yield better chips
In the down economy, "design for manufacturing" hasn't yet had the opportunity to live up to its billing as the next big avenue of growth for the EDA industry. Still, experts say, it's only a matter of time before the semiconductor industry turns around and the DFM space takes off. And they are looking to "probabilistic" or statistical timing as an area that will vastly improve chip performance and chip yield, establishing DFM as an imperative market and perhaps lead to the next big ERA in design and EDA retooling starting in 2005.

"Probabilistic" or statistical timing analysis is generating a huge buzz in the academic world, and EDA vendors are just starting to look at its commercial possibilities. They say a new timing tool, would likely mean a new methodology — a new synthesis tool, place-and-route tool, extraction and others.

Researchers say it would mean a dramatic boost in yield and chip performance and would give them the ability to accurately predict upfront yield for a given chip running at given performance level. It would also let an ASIC vendor charge greater fees for higher performance ASIC runs at the expense of yield.

Statistical timing analysis is a next-generation timing technology that promises to be far more accurate than today's static-timing analysis (STA) tools — accounting for silicon process variables and giving designers an upfront view of chip yield vs. chip performance.

"More than any other time I can think of, the gap between designer needs, corporate CAD and the EDA industry is the largest I've ever seen," said Kurt Keutzer, professor of electrical engineering at the University of California Berkeley. "Designer needs are ahead of corporate CAD, corporate CAD needs are ahead of anything the EDA industry is able to provide. If we were in a better economic environment that would be more apparent, but we're still in the 'Nuclear Winter' of the semiconductor industry."

And, said Keutzer, innovation of statistical timing analysis is one niche in the DFM space that needs to be filled to close that gap.

Until now, statistical analysis has been applied to analog design for modeling RF circuits.

But Keutzer and a growing number of researchers, believe that statistical timing will become critical for pure digital design, especially as processes descend below 90 nanometers and more 300-mm fabs and newer processing equipment come on line. Statistical timing was the main topic at last December's timing conference, the Tau Symposium.

The general argument is that today's workhorse STA tools method is overly conservative and derives timing based on pessimistic and inaccurate worst-case gate and interconnect models.

This overly conservative static-timing approach chiefly sacrifices performance and promises to become more conservative and sacrifice even more performance as process geometries shrink. Researchers also believe that static tools, even in their conservative approach, simply are not accurate enough — ultimately causing respins, which ultimately lead to product delays.

Indeed, in a DAC paper last year entitled, "A General Probabilistic Framework for Worst-Case Timing Analysis," study paper authors Michael Orshansky, U.C. Berkeley research scientist and lecturer, and Keutzer conclude that static timing underestimates the value of a typical clock period, overestimates worst-case timing behavior, requiring expensive redesigns, and is incapable of providing accurate parametric yield information. (Their paper can be found in pdf form).

Researchers argue that static timing is deterministic in that it uses fixed delays for gates and traces and doesn't consider statistical variations in the underlying silicon.

In the current STA methodology, best-case, worst-case and nominal parameter sets are derived using Spice simulation. The STA tool then runs several times to report the resulting numbers. But given multiple variables in processing on top of issues such as such as climate can make best-case and worst-case parameters completely miss the actual performance and reliability of a chip.

Researchers said that a statistical approach would use random variables, rather than fixed delays and would produce a statistical distribution, rather than best-case and worst-case models.

The technology would also tell an engineer the percentage of circuits that will run at a given speed-allowing the engineer to adjust timing criteria to reach the acceptable mix of yield vs. performance for a given chip design.

A commercial statistical timing tool would then seemingly allow the designer to make the decision to sacrifice chip performance in favor of higher yields and vice versa. And the technology, simply because of its closer link to processes, would likely speed overall development time and improve yield — some say improving both by as much as 25 percent over today's marks.

"Statistical timing is truly one of the grandest challenges of EDA," said Chandu Visweswariah, staff member at IBM Corp.'s Thomas J. Watson Research Center and widely deemed the leading expert in statistical analysis. "The number of timing runs you need to perform on a chip is increasing all the time. It used to be we did a nominal run, then we did best and worst case, then we do different corners, then we do a separate NBTI, and then one for coupling noise. Anything we can't model or show uncertainty gets bundled into some worst-case condition, which eventually leads to pessimism — we are not managing risk very well. Therefore I believe the era of probabilistic design is here. You don't optimize your circuit and say 'did the delay or clock frequency improve?' You ask yourself 'did the probability of a working part improve?' Everything will be driven by probability in tomorrow's methodology.

A simple example of where a statistical method would differ from an STA method can be found, Orshansky said, in the way the methods deal with the probability that a particle, such as speck of dust, would land on a trace during manufacturing.

In today's STA this occurrence would be accounted for as a "stuck-at" fault, creating chip failure, and would require no further analysis. A statistical tool would account more accurately and realistically the likelihood that the particle would simply lower performance on the circuit and estimate how much it would lower performance.

Orshansky points out that how much it slows performance down or whether the particle causes catastrophic damage will likely depend on where this speck of dust lands. The probabilistic approach would address these nuances in timing, where a static tool would simply say "rejected" and then require another specialized tool or add-on and at least one more static-timing run to see it as a delay fault rather than a stuck-at fault. Statistical tools would also likely lessen or eliminate the need for fault-analysis tools in the design process and speed up manufacturing.

That's just one of many advantages statistical timing would afford over static timing, Orshansky points out, and there are many academic papers describing the advantages and different strategies being formulated for statistical analysis.

Hurdles
While academia is in agreement that the statistical method is the way to go, the researchers are debating which approach would be best.

Keutzer said that the furthest along in statistical analysis is indeed one of the most advanced EDA companies in the world, IBM. The company makes its own tools for its own customers to design to its own bleeding-edge silicon processes.

Because IBM tool developers are close to and have access to critical process data is arguably one of the main reasons IBM is No. 1 in market share in the ASIC business as well as in process innovation.

Indeed, Visweswariah, whom Keutzer calls the top researcher in this area, is also the furthest along in statistical timing research. In a paper at June's Design Automation Conference, Visweswariah is expected to describe how IBM is already starting to use statistical timing. The technology will seemingly help IBM build on its lead in the ASIC world and strengthen its position in microprocessors and custom chips.

Visweswariah is pioneering a multifaceted approach that derives a statistical near-golden model of a circuit verified by highly constrained Monte Carlo simulation. "We use the Monte Carlo as a golden or semi-golden result with which to compare these other statistical techniques," he said. "Monte Carlo is one arrow in our quiver; our method employs several other mathematical methods — it will all be in the paper at DAC."

Berkeley's approach, according to Orshansky, is looking at boundary conditions.

"My perspective is that in order to make it a commercial technology, you need to come up with an efficient and therefore analytical probabilistic computation," said Orshansky. "My view is that we cannot accurately predict the distribution analytically but we can bound it." That, he said, would be many times more accurate than static-timing tools and would look at variations within a single die-something static tools don't do.

Other prime academic research in this area is being conducted at the University of Michigan by David Blaauw and Bhavana Thudi.

The Commercial Market
The big EDA vendors believe the technology is intriguing but they have only recently begun to look at the area and they say commercial tools are couple of years away.

Cadence Design Systems Inc. is doing research in the area and plans to derive a whole new tool. Cadence's work is similar to that of Orshansky. Where Orshansky proposes replacing each delay with a distribution of delays, Lou Scheffer, a fellow at Cadence, proposes replacing each delay with a small equation describing how it depends on the process conditions.

Meanwhile, it's hard to determine whether Synopsys Inc. has anything going in this area or is keeping its work in the statistical area close to vest.

Bijan Kiani, vice president of marketing for nanometer analysis and test, said the company is "pouring many research dollars" into improving static-timing analysis. He said the company will continue to improve its PrimeTime static-timing tool and will likely add statistical timing via add-on improvements to PrimeTime. That tool owned 71 percent of the static-timing analysis market, according to Gartner Dataquest's 2001 EDA market study, and Synopsys obviously wants to retain that lead.

Static timing has traditionally been a one-company market. ViewLogic's Motive, for example, was the de facto standard timing tool before Synopsys introduced PrimeTime and later bought ViewLogic and killed the Motive product. Other timing tools are on the market but none has significant market share.

Indeed, design engineers typically converge on using one timing tool. As a result, the rest of the EDA industry and library vendors are forced to ensure their tools and IP work tightly with that timing tool.

It is also the tool that other tools are built around. Thus, if the timing tool changes significantly, it means that other tools will also need to change or be drawn from scratch. Thus, a new static tool likely means a new retooling and new era for the EDA industry. Vendors and academics predict statistical timing tools will hit the market in 2005 and the subsequent flow built around those tools will be targeting the tricky issues of 65-nm processes, which should be coming on line after 2005.

Scheffer said extraction, delay calculation, libraries and library generation and delay fault calculators would have to be reworked and likely rewritten to work with statistical timing.

"It remains to be seen what impact this would have on optimization and synthesis and possibly on place-and-route tools," said Scheffer, who noted that Keutzer and Orshansky were seeking a research grant from the Semiconductor Research Corp. to study synthesis/optimization for statistical timing analysis. Keutzer said the proposal made it to the final round but the SRC ultimately rejected it in early March.

Orshansky said that he hoped eventually to see his research applied in the real world and become a commercial product. And he has not thrown out the idea of launching a future EDA startup in this area.

Perhaps most difficult in getting this new era under way is that it will require unprecedented cooperation between EDA companies and silicon vendors, as many formats and process information would need to be exchanged freely, hopefully with the spirit of rebuilding the design industry as a whole.

Orshansky points out that at the least foundries would have to agree to perform or provide data on statistical process characterization; library companies would have to create or add statistical libraries to existing library information; and EDA and perhaps silicon vendors would have to create statistical models for timing analysis.