News & Analysis
SoCWare multimode transceiver in next integration stage
Mattias Wgman
2/7/2003 2:54 PM EST
This is the third status report from the Swedish Socware Transceiver Demonstrator Project -- SoCTRix. Since the last status report in October 2002 the activities have continued very successfully within all technical fields addressed by the project. Discussions with new potential partners from Sweden, Germany, US, Japan, and Taiwan are ongoing. New partners that have joined include Catena (Holland), the Swedish Defense Research Agency and the Norwegian University of Science and Technology. Existing partners are Samsung Electronics (Korea), Agilent Comms EDA (United States), Industrial Technology Research Institute (ITRI in Taiwan), Chartered Semiconductor (Singapore), Via Technologies (Taiwan), ARC International (England), and BitSim (Sweden).
During the past three months, the system design team has focused on finalizing the Air-Interface Specification and Baseband Signal Processing Specification for the multi-standard transceiver. The final standards include IEEE802.11a,b,g and WCDMA, FDD-mode. An implementation proposal for antenna front-end has been finalized and is based on differential antennas and antenna filters.
Separate receive and transmit antennas are used to minimize front-end losses due to switches. Discussions with a third party company about differential SAW front-end filters for the WCDMA-mode have been initiated. Further, transmitter and receiver dimensioning for the OFDM-based standards are underway. The associated Ph.D. students have continued their research, in cooperation with the SoCTRix project, in partitioning WCDMA receiver requirements and modifying the 802.11b baseband algorithms to enable a common clock with 802.11a, closely related to the transceiver frequency.
RF IC design
With the MPW1818-RF tapeout in December, the RF IC design activities have completed the process exploration phase. In MPW1818, the following RF-blocks were included: phase locked loop; transmitter variable gain amplifier; transmitter baseband reconstruction filters; polyphase filter for I/Q-generation at 5-6 GHz; 5-6 GHz VCO; and capacitors and varactors for characterization purposes.
The goals of the initial phase of the RF IC design, namely to establishe the design flow and then to assess the properties and capabilities of the design kit and the Chartered Semiconductor process, have been achieved. In addition, most of the main blocks of the transceiver have been addressed and have provided important feedback to both RF IC and system designers. For some of the blocks, e.g. the PLL, the designs made so far will form the base for the continued work towards the final design, whereas others will need to be addressed with new topologies.
The RF IC design will continue with higher level of integration, e.g. LNA-Mixer-PLL, focusing on optimal "sub-system solutions" while targeting the final specifications. This implies a significant increase in complexity of the design compared to the previous phase.
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| Figure 1: MPW1818 RF-chip layout |
The next design period will target the MPW1822 in the Chartered process by June 2003. The plans for this tape-out includes following blocks:
Baseband design
Since the last status report the algorithm team has been developed and has implemented the following in Agilent's ADS/Ptolemy software:
Engineers from BitSim have contributed with their own work in the development of these algorithms. The algorithm development will continue with 802.11a packet detection, carrier frequency offset estimation/correction, and timing detection.
Digital design
The digital design team has heavily focused to get the design flow working. The target design was implementing an 802.11a transmitter.
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| Figure 2: MPW1818 Digital chip layout |
This design includes a model of a complete 802.11a transmitter data path in Agilent ADS and the digital design of the sub-blocks in Chartered's 0.18u process. The design was taped out at the end of December. Activities for the next three months will be to focus on the building block implementation for the multi-standard transceiver that is the ultimate target of the project.
Signal processing
The work within the area of digital correction of analog errors is ongoing. During the past months the group have focused on power amplifier modeling and quadrature error correction. Algorithms to correct for receiver and transmitter I/Q amplitude and phase balance have been developed.
Mixed signal design
Since the last status report the mixed-signal team has worked to design a large part of a 10-bit 80 Msamples/s pipelined analog/digital converter, taped out in December. Near term, the plan is to complete the documentation and to create a test environment for the ADC and then test the device.
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| Figure 3: MPW1818 Mixed signal chip layout |
The next step for the mixed signal group is to start converging towards the design that will meet the requirements in the final transceiver implementation.
For more information, please visit the acreo and Socware sites.
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