DATE attendees ponder 90nm test strategies

DATE attendees ponder 90nm test strategies
The Design Automation and Test in Europe (DATE) conference, taking place this week in Munich, Germany reveals a surprising profusion of advanced concepts in circuit and system design. Perhaps one lesson of the SoC era will be that nothing can exist as an isolated specialty. For example, an entire day at the conference is being set aside to explore the concept of Ambient Intelligence described by organizers to be "a new paradigm for user centered computing and interaction, combining aspects of ubiquitous computing, natural interaction, and intelligence."

The enormous capacity of SoC chips to integrate diverse functions makes wide ranging design ideas necessary, and the SoC net has also snared the test and measurement requirements of system and chip design. Once an afterthought, test and measurement now glows with a remade image due to its integration as a critical component in SoC design automation. After all, why design in a pallete of exotic capabilities if the whole thing is going to founder on some neglected detail?

These days, it is getting difficult to distinguish the test engineer from the circuit designer. This week's In Focus features a number of contributors discussing the new rubric of the SoC design era: Design for Test. We lead off with a paper from DATE by engineers at Intel Corp., Bill Grundmann, Rajesh Galivanche, and Sandip Kundu, who give a rundown on what awaits circuit designers as technology moves beyond the 90 nanometer node. Power dissipation has become a clock frequency limiter, leakage current limits low-power designs, and while the absolute number of gates available on a chip climbs, the actual gates-per-cycle continues to decrease. In their paper, titled, "Circuit and Platform Design Challenges in Technologies beyond 90nm", they suggest that on-chip sensors that monitor a variety of design parameters such as interconnect delay, power dissipation and leakage current may be a new aspect of built-in test that will become essential.

In a hot topic DATE session called Value for Test, engineers from Philips Research Laboratories, LSI Logic Corp and IBM Deutschland Entwicklung GmbH, offer their experiences in debugging specific systems. Philips' principal scientist, Erik Jan Marinissen and Bart Vermeulen, discuss a test method that helps reduce time to market by using existing scan chain access to debug prototype silicon. Robert Madge from LSI Logic's Product Engineering, explains how understanding raw test data results can be crucial for quality and cost reduction in manufacturing. And, IBM's Michael Kessler and Michael Muller give a breakdown of their experiences building upon the success of generations of testing techniques for the zSeries 900 (s390) - a multichip module targeted at "... customers with mission critical applications are highly dependent on the premium quality of the machine, 365 days a year, 24 hours a day." Their paper details the testing of the 2000 generation consisting of 20 central processors, two cache controllers, 8 cache chips, 4 memory bus adaptors and a clock chip.

One notable trend at the conference is the increasing use of on-chip circuit components to provide self-testing functions or monitor circuit parameters. The technique is becoming essential for complex SoC. Called infrastructure IP, the approach is now fueling a significant trend away from relying on external test equipment to locate errors on an SoC. Future technology generations may have to rely almost totally on this technique.

The right infrastructure

"Looking into the far future with chips measured, maybe, in cubic millimeters or cubic centimeters -- how are we going to test this massive complexity from outside , asked Salvador Mir, one of the DATE organizers and the reliable mixed-signal systems group leader at TIMA Laboratory, Grenoble, France. "With so much intelligence put inside, no doubt the chip will be able to do it itself and the right infrastructure will need to be there."

With increasing silicon real-estate available with each new technology generation, the question of whether the infrastucture IP trend may eventually replace today's test equipment became a significant issue at the conference. "The use infrastructure IP for test and measurements has become essential," according to Liaison Chair IEEE, Yervant Zorian of Virage Logic. "While using additional logic on-chip for test purposes had started long ago, such as for scan or JTAG, the continuous increase in such circuits has increased the chances to simplify the test equipment." However Zorian does not believe that external test equipment will ever be replaced. "Several key functions in test, diagnosis and measurement have moved from external equipment to embedded infrastructure IP. This trend is expected to continue by moving more of the repair fault tolerance and reliability functions into the SoC," he explained.

Some of the committee members also discussed the blurring boundary between hardware and software errors and the problems being created by the increasing use of reconfigurable elements and reconfigurable processor cores. Reconfigurable blocks are becoming popular with SoC designers as a means of insuring the integration of IP. But they also pose more problems for the test engineer.

"Reconfigurability makes hardware test a lot more complex, since now you need to test the circuit for all possible configuration," said Zorian. "This is very time consuming and increases the cost of hardware test; whereas testing for software errors remain specific to a single configuration and hence can be contained better."

Could configurable blocks aid the test engineer by being used as a flexible method of downloading a variety of self-test functions onto an SoC? "We can look at that by considering the different types of tests and defects/errors," said TIMA Laboratory's Salvador Mir. On the one hand, reconfiguration leads to an increased functionality and results in a more complicated functional test. "This is specially true for concurrent on-line testing allowing the detection of transient hardware errors or software errors. The reconfiguration leading to self-test functions can be advantageously exploited in the case of semi-concurrent or non-concurrent on-line testing approaches, but the detection of all transient errors may not be ensured," he said. For permanent errors due to physical defects, structural testing can benefit from reconfiguration. "While the number of possible defects does not significantly increase with reconfiguration possibilities, these functions allow for further alternatives to detect faults," he added.

Committee member, Erik Jan Marinissen, sees that reconfigurability might be used for taking care of design errors but he doesn't see it for taking care manufacturing defects. "That would require that you test your chips and you find that your chips in principle are ok, but there is one copy out of the million or so that has a manufacturing defect and you are going to do something special with reconfiguring that one, so that you can still sell it . Perhaps that will come in the future, but not as an individual basis, but more with using fault tolerance, so we build an outer infrastructure on the IP that will mask the faults," he said.

90nm circuit defects

As VLSI technology rapidly approaches nanometer dimensions, new on-chip sensing and fault analysis systems will probably be needed in addition to traditional test methods. The reason is the occurrence of new failure modes introduced by size scaling. "Ninety nanometer circuits are introducing new types of dynamic defects that can only be tested at high speeds via embedded test and measurement circuits. The high speed and RF blocks will necessitate more sensors on chips," said Zorian.

And, TIMA Laboratory's Mir pointed out that the relative importance between defects will change. He expects crosstalk sensitivity to become very hard to deal with and dynamic test methods will be most relevant. "It appears clear that MOS device and interconnect technology are radically changing as you go deeper into the nano world, such as three-dimensional triple-gate transistors and interconnects making much use of CMP and copper and low-k materials."

He noted that as new failure modes turn up, new self-test opportunities should hopefully arise. But nothing can prove that some effects, that may not have an instantaneous impact on functionality but can lead later to a catastrophic failure, remain undetectable. "However, we can somehow put our minds at ease by thinking that silicon can basically perform at small scale all interface functions between physical magnitudes and electrical signals, thus leaving very little chance for undetectable effects," he said.

"In most of these 90nm dimensions, we see new faults occurring," noted Marinissen. In manufacturing test, most of the logic testing was based on the stuck-at-fault model. But doesn't take into account that if a signal arrives late on the chip, it might cause problems. Now with 90 nm technology everything gets smaller and more sensitive to effects — for example, things that we previously didn't care about such as crosstalk and soft errors. Plus, everything gets faster, so it is far from realistic to say we have can depend on the static fault model that doesn't take timing behavior into account at all. Increasing companies are requiring more difficult tests."

Besides the DATE presentations, other contributors to this In Focus report get into some of the new challenges facing both SoC designers who need to add design-for-test to their set of skills and test engineers who must devise new approaches.

Mentor Graphics' Greg Aldrich and Ron Press offer their view on how manufacturing tests and DTF will change as the industry moves to nanometer design processes and what role BIST and embedded test will play. Ajay Khoche, DFT scientist at Agilent Laboratories, discusses the effects of bandwidth matching on DFT, scan test, EDA, and ATE.

Meanwhile, Bernd Koenemann, a fellow at Cadence Design Systems, looks into the importance of "realizing the full potential of a comprehensive, structure-oriented DFT strategy as an engineering interface platform" and engineers Rohit Kapur and Mouli Chandramouli from the Test Automation Products Group at Synopsys, Inc., offer their perspective on using structured test methods instead of functional testing in high density devices. The results, they say, can be a significantly reduced cost of test.