Taking the pain from design for manufacturability

Taking the pain from design for manufacturability
A seldom-used EDA acronym, DFM (Design for Manufacturing), is being defined today as the missing link between design and manufacturing. DFM is more than the buzzword du jour, however. Increasing semiconductor manufacturing expenses continue to represent real economic burdens measured in billions of dollars every year. Some 130-nanometer mask sets have hit the $1 million mark, and 90-nanometer masks are expected to cost even more. Lost yield regularly costs companies millions of dollars per year per production line. The chance for first silicon success is fleeting as design capabilities continue to outpace manufacturing realities.

Historically, designers have not been held accountable for DFM, because time-to-market and die size are more easily predicted and calculated than yield figures, which are only reliable after the start of production. A primary example of the resulting designer oversight is the standard cell, the building blocks of modern digital IC design. Standard cells are the interface from design to manufacture, blending logic design information (netlists), design trade-offs of performance, power, area, and yield (cell template), and manufacturing process requirements (design rules). These standard cells are duplicated many times throughout a design, and routinely determine the manufacturability of an IC. Standard cell design should be the focus of a move to manufacturability.

While minimum design rules and area-minimizing design practices are tried and true, yield-improving "recommended" design rules and other DFM design practices have also long been available. Examples of these DFM practices include decreasing the likelihood of contact/via failures by increasing contact/via metal overlap, using wider and longer metal end-of-line extensions, and using redundant vias/contacts. The number of critical features can be reduced by limiting poly and diffusion routing, using straight transistors, minimizing the number of vertices, and avoiding forbidden pitches.

Approaches to design rules

Optical and process correction (OPC) methods are a critical aspect of improving yield. Integrating OPC-friendly design styles will not only reduce OPC and mask-making cycle time and cost, it will also ensure best silicon performance. (DFM OPC recommendations include: Use rectangular line-ends, forbid circle or oval shapes, avoid short-cropped corners, small zig-zag patterns and small jogs.)

With plenty of approaches available, here's the multi-million dollar question: Why don't yesterday's designers use DFM practices today? The excuse is area: blanket adoption of DFM practices at the standard cell level could result in a design area penalty of 30 percent or more. Fortunately, blind use of all DFM measures is not necessary; however, standard cell designers require an automated way to analyze DFM options at the cell level to be able only to implement those that do not increase area. Studies have shown that 70-80 percent of the DFM practices can be implemented without an area penalty, which should result in an estimated 5-10 percent yield increase in addition to lower mask costs and faster silicon.

The design-to-manufacture chasm is growing at an alarming rate as chip size and complexity increase and process geometries decrease, and as market pressures increase and product life-cycles decrease. The emerging state of semiconductor production demands that designers take manufacturability into consideration up front, rather than leaving it as an expensive and time-consuming afterthought. Successful companies Don't Forget Manufacturing. Unsuccessful companies will continue to design without regard to the layout on masks and wafers, and for them, DFM will take on a whole new meaning: Desperate For Money.

Dan Nenni is vice president of sales and marketing at Prolific Inc.