EDA isn't just ASICs

EDA isn't just ASICs
We're doing a lot of coverage on the move to 90 nanometers this year, but most of our readers, and most EDA users, aren't going there personally. There are far more people designing FPGAs and pc boards than cutting-edge ASICs and systems-on-chip. How is the EDA industry serving this vast mainstream?

Not very well, says Nick Martin, founder and joint CEO of Altium Ltd. (formerly Protel International). In a recent EDA Views column at EEdesign, Martin noted that the big EDA vendors are snapping up smaller providers and focusing on a handful of big accounts, pushing aside "marginal" customers who don't have big budgets or leading-edge ASIC projects.

Martin said that the costs of 0.13-micron, 300-mm wafer design "eliminate perhaps up to 80 percent of designs from ASIC consideration." Wally Rhines, Mentor Graphics CEO, said much the same in an EE Times article appearing on Jan. 6.

"We've reached the point where the typical venture capital investment is not going to tolerate $20 million before first silicon," Rhines said. "That's causing things to happen at the low end, where a lot more people are moving to FPGAs."

It's easy to see why most EDA vendors are focusing on nanometer IC design. That's where the money is. That's where design teams are willing to pay $50,000, if not $500,000, for a tool that will help them get to market faster and avoid silicon respins.

But what about the tens of thousands of designers who need affordable tools for FPGAs or pc boards? Relatively little effort is going into providing them, but they're needed. And just as in the ASIC world, advancing technology is creating a need for new EDA tools.

As FPGAs grow in complexity, the problems of high-end ASICs start to appear. Verifying a million gates is a challenge, whether they are ASIC or FPGA gates. Assertion-based verification, physical synthesis, silicon virtual prototyping, power analysis, and other technologies developed for high-end ASICs will need to be brought into the FPGA world, and made affordable.

Pc board designers need better tools to manage growing signal-integrity problems, both before and after board layout. Tools are badly needed for RF multichip module design. Chip, package and board designers need to work together to understand what happens when you put 250-MHz chips with 2,000 I/Os on a board.

Let's hope the EDA industry isn't just about ASICs in 2003.