Successor to Verilog approved as Accellera standard

Successor to Verilog approved as Accellera standard
SAN JOSE, Calif.—The next-generation version of the Verilog language has been approved as a standard by the Accellera organization. Called SystemVerilog, the language blends Verilog, C/C++ and an assertion capability from Co-Design Automation Inc.'s Superlog language to provide higher levels of abstraction.

The watch has begun to see which electronic design automation vendors will support SystemVerilog, and when. At a briefing next Tuesday (June 11) at the 39th Design Automation Conference (DAC), Accellera is expected to announce EDA vendor endorsements of the new standard.

Dennis Brophy, Accellera chairman, said he expects a "depth and breadth of commitment by the industry" because of strong user demand for SystemVerilog. "People are anxiously waiting for support," he said.

The Accellera committee that approved the standard included Avanti, Cadence, Co-Design, Fintronic, Forte, Get2Chip, Hewlett-Packard, LSI Logic, Mentor Graphics, National Semiconductor, Real Intent, Synopsys, Verisity and Verplex, though not all will necessarily embrace the standard. Synopsys' support is a big question mark, as it is pushing OpenVera 2.0 as a new assertion language standard.

The make-up of SystemVerilog was outlined in March at the International HDL Conference. It includes interfaces that allow module connections at a high level of abstraction, C-language constructs such as globals, and an "assert" construct that allows property checking. It also includes the synthesizable subset of Superlog.

Discussion points

The assert construct was still under development in March, but is now completed. Even so, "there are still some technical issues the team needs to discuss," Brophy said.

Accellera wants SystemVerilog's "assert" construct to be as close to IBM Corp.'s Sugar language as possible, Brophy explained. Accellera approved Sugar as a formal property language in April. However, Accellera also wants to guarantee backwards compatibility with previous versions of Verilog.

"That's placed some constraints on the way we actually express certain things in the assert construct that might differ a little bit from the proposed Sugar standard," Brophy said.

Also unresolved in March was the proposal to allow SystemVerilog users to instantiate modules with implicitly named ports. That proposal was passed by Accellera, Brophy said. "It simplifies quite a bit of Verilog code," he said. "You no longer have to connect things up wire-to-wire. Named objects can be connected, and it can be done implicitly."

In addition to next Tuesday's briefing, Accellera will present information about SystemVerilog at a membership meeting and hold a designer's forum meeting at DAC next week.