Unified tools rev embedded-processor design

Unified tools rev embedded-processor design
SAN MATEO, Calif. — With ambitions to automate performance modeling and embedded processor design, an EDA startup with roots in Aachen University in Germany will make its official public debut and product introduction at the 39th Design Automation Conference in New Orleans.

Lisatek Inc. was founded last year, but the seven-person company did not make its software widely available until now, after securing funding from S-VC, the venture capital arm of German Savings Bank.

The company's tools, originally developed at Aachen University of Technology, promise to automate embedded-processor design, both hardware and software. That has been a vastly underserved design area until now, said Lisatek cofounder Uri Mayer.

"We think that many people that wouldn't touch processor design before will now begin to look at it," he said. "To many people it was a very big problem to design an embedded processor. It was not that they didn't have the knowledge, it was that they didn't want to put in the effort in tool generation."

Mayer, a one-time Cadis/Synopsys executive, said that while other companies offer pieces of the embedded-processor tool flow, no one has offered an independent, unified tool suite. ARC Cores Ltd. and Tensilica Inc. have similar tools, but only for use with their respective proprietary architectures, he said.

Lisatek offers three tools that together, the company said, will let users simultaneously design the hardware and software of an embedded processor with a proprietary C++-extended language, and then pass VHDL and C to traditional hardware and software design flows.

Inside the tool suite

The company's flagship tool, Edge Processor Designer, is essentially a tool suite itself, comprising three simulation tools and 15 tool and model generators.

In the Edge Processor Designer, users describe the instructions of their embedded processor using the company's proprietary Lisa, or Language for Instruction Set Architecture. Mayer said anyone familiar with C can learn the language in one to three days.

Mayer said Lisa enables designers to create performance models for all types of embedded-processor architectures, including microcontrollers, digital signal processors, network processors and application-specific processors.

"You design the instruction set and architecture of the processor simultaneously," said Mayer. "You run the application on the instruction, so you see how effective your application and instructions are. If you have an instruction you never use, you can throw it away." In this way, he said, "you optimize your instructions for your targeted application."

Mayer said the tool then creates a cycle-accurate model of the processor being designed.

The company's second tool, the RIM Software Designer, generates a linker, a compiler, an assembler, a disassembler and a debugger for software design to go with the model.

RIM also has a unique instruction-set simulator called just-in-time cache-compiled simulation (JIT-CCS) that combines the performance of traditional compiled simulators with the flexibility of interpretive simulation. Lisatek's paper describing the JIT-CCS will take the embedded-track best-paper award at DAC.

VHDL left outside

Once users are happy with their model, they can direct Lisatek's third tool, the Hub System Integrator, to generate VHDL for most of the processor and integrate it into its targeted system-on-chip (SoC). But the tool does not generate VHDL for the data path of the processor, leaving that for downstream EDA flows. A future version will generate SystemC.

The latest version of Hub includes a multiprocessor simulation capability to verify heterogeneous systems of embedded processors with a user-defined number of debuggers. It also has a retargetable simulation application programming interface for customizing and interfacing with different SoC design environments, including Synopsys' CoCentric System Studio and Mentor's Seamless co-verification tools.

Lisatek's unified product suite runs on Solaris 2.7 and 2.8, Linux and Windows NT/2000 platforms. Module pricing starts at $50,000.

Mayer said the Lisatek technology could be extended in the future to help with the design of SoC devices.

Mayer, who is Lisatek's president and chief executive officer, said the company would eventually like to consider an initial public offering but that it is far too early to think when that would take place.

The company plans to build staff, especially in research and development and support.

Mayer said early adopters of the technology have seen great speedups in simulation time and time-to-market. "With our tools," he said, "customers have slashed their embedded-processor design cycle from 18 to 30 months to just one to two months." Simulation time has been reduced, on average, from three days to just an hour using the Lisatek flow, he said.