System-level design brings new methodology

System-level design brings new methodology
Here we are, back in New Orleans for another Design Automation Conference. Most DAC visitors arrive in "tool-browsing" mode, casually looking for a faster simulator, more accurate timing extractor or improved floor planner.

Very few, however, will tell you they are in search of a better design methodology. After all, many logic designers have used the "RTL-to-gates" design methodology throughout their careers, and it's hard to imagine not starting at the register-transfer level. But applying the right design methodology can literally mean the difference between success and failure.

While we all know that tools impose constraints on our ideal methodology, few realize that design languages impose large constraints on what tools can do. New design languages offer the industry an opportunity to advance design methodology to fit today's modern challenges. It's the methodology that's important, not the syntax.

Thus, if you have come to DAC looking for relief, you cannot afford to ignore system design methodologies and the languages that enable them. As high-tech companies replace fear with cautious optimism, they are starting the next generation of designs, characterized by all the things VHDL and Verilog were never designed to address. The integration of multiple processors running embedded software, analog baseband, RF and optics-all powered by a small lithium battery-is clearly beyond HDLs.

The complexity of design trade-offs among so many dimensions cannot be processed through the tool flow, because that information has had no home until now. The plethora of system design language choices has spawned controversy and confusion. Whether the syntax looks like C, Verilog, VHDL or UML, most options share a common goal -- to transition functional design from the minutiae of Boolean logic, wiring and assembly code up to the level of the designer's issues.

Thus, functionality becomes modeled as an architectural interaction of behaviors, protocols and channels. This is great, except that most languages handle only digital functionality and cannot comprehend trade-offs of power, timing, packaging or cost.

While the debate goes on over which languages will succeed, yet another language option has been quietly progressing with a larger goal. This emerging language, whose requirements were specified directly by system and semiconductor companies over the past five years, embraces the concept that system-level design constraints are intrinsically multidimensional.

It captures the constraints on timing, latency, power and even functionality, and it can relate one with the other. It spans abstraction levels and semantic domains, allowing the designer to see how a change in one view affects the others. And it lets designers model functionality in the syntax of their choice.

The language is Rosetta, sponsored by Accellera International. Rosetta is no longer just good theory; it exists now, with commercial tool support, and can be seen on this year's DAC show floor at the booths of such vendors as EDAptive Computing, FTL Systems and Ashenden Designs. See for yourself at DAC, or visit the web site of Accellera's System Level Design Language committee.

Steven E. Schulz, co-founder of the Vital and SLDL standards initiatives, has served on the boards of Accellera, VHDL international, Semiconductor Research Corp. and the EDA Industry Council. He is currently the vice president of corporate marketing for BOPS Inc.