Alatek offers network-based verification system

Alatek offers network-based verification system
HENDERSON, Nev. — Alatek Inc. is taking the wraps off of its Comulator N2.1 platform, calling it the first networked-based verification system that combines acceleration, emulation, and co-verification without requiring a separate chassis. The platform consists of boards that plug into Sun Ultra and Sun Blade workstations.

Alatek, a spin-off of Aldec Inc., specializes in hardware-assisted verification. Aldec resells Alatek's current Hardware Embedded Simulation (HES) acceleration boards bundled with Aldec simulators, but users can purchase the boards directly from Alatek for use with other simulators. Comulator is available only from Alatek.

To create Comulator, Alatek added Emulator for Multiple Applications (EMA) boards that piggy-back onto the HES acceleration boards. The company also developed a new version of its Design Verification Manager (DVM) user interface software, and boosted the capacity of the HES boards, which can now include up to two Xilinx Virtex 6000 FPGAs. Finally, users can plug in MIPS or ARM 9 boards for hardware/software co-verification.

"Because everything is contained in a standard workstation, we believe we have the first network-based platform," said Lori Swenson, director of strategic marketing at Alatek. "We also believe we have the fastest co-verification on the market."

Swenson said that the HES acceleration boards work with any simulator that supports the standard Verilog PLI or VHDL VHPI interfaces. Each board supports up to 1.6 million ASIC gates, yielding 12.8 million gates for the maximum eight-board configuration. Acceleration speeds are 10 to 100 times faster than RTL simulation, the company said.

For faster performance, users can turn to emulation, which runs without connection to an HDL simulator. Alatek claims emulation speeds of 100,000 cycles/second to 100 million cycles/second, which it characterized as being up to a million times faster than RTL simulation.

The EMA boards contain FPGAs that are used for data management, but the design is actually loaded into the FPGAs on the HES board, providing an emulation capacity of up to 12.8 million gates. The EMA boards also contain up to 1 gigabyte of on-board memory, as well as a variety of interfaces for plugging in external devices, including USB, Ethernet, PCI, and VGA.

What users don't get with emulation is source-level debugging, although a waveform display is provided. Both the acceleration and emulation run at the gate level, although RTL code can be downloaded and synthesized.

Co-verification claims speeds of 1,000 to 10,000 cycles/second. For co-verification, software is run directly on the MIPS or ARM boards that plug into the EMA boards; the MIPS and ARM boards will be available this month. An EMA board with an embedded MIPS processor is planned for June.

The enhanced DVM software helps users prepare designs for acceleration or emulation, and allows partitioning of designs across multiple FPGAs. The Comulator can support a team design over networks, and runs in Unix, Linux or Windows environments.

Alatek says price is a major selling point of Comulator, which starts at $60,000 for a system that includes one HES and one EMA board, DVM software, and a Sun Blade 1000 workstation.