Can you afford not to go to DAC?

Can you afford not to go to DAC?
Technology companies tend to not be very good at cost accounting, at least as far as the design process is concerned. In a way this is understandable. More than a few companies have gone out of business by trying to apply Industrial Age metrics to their Information Age companies. The old gates-per-week metrics, sometimes used in ASIC design, is a good example. Most designers know how to set their synthesizers to effortlessly produce the maximum amount of gates, giving them plenty of time to find a job in a company that takes design seriously.

On the other hand, avoiding any type of measurement system is a recipe for disaster, especially today. The 2001 International Technology Roadmap for Semiconductors (ITRS), previously known as the Semiconductor Roadmap, tackled this very issue and ultimately produced the SoC Cost Design Model. The Design Technical Working Group (TWG) stepped back and looked at the entire design cycle, avoiding the micro-managing metrics that have proven detrimental to design innovation.

The TWG looked at the raw cost-in real out-of-pocket money, not including the questionable time-to-market costs that vendors have been touting since the mid-1980s-in manpower, overhead and EDA tools needed to complete a five million gate ASIC design for a PDA. The results should be shocking to any accountant or CFO.

For example, while Company A may be happy with the tried and true basic RTL methodology it has used for the past ten years, Company A's competition may not have been quite so resistant to change. While that PDA design costs Company A somewhere around $342,417,579, the competition has only spent $15,066,373 on the same design. This data doesn't help Company A's competitive position.

Click here for SoC cost model

While this example serves as a worst-case scenario, any company that is far behind the curve is either no longer in business or is now selling software. Still, the SoC Cost Design Model tells us that significant design innovations are being introduced at two-year intervals. Companies cannot afford to stay with an obsolete tool while the competition jumps on implementing the upgrades.

Even the conservative position -- not taking into account phantom issues like "late-to-market" -- tells us that missing out on a tool change will cost a month's design time. Straight math shows that a company that has remained on top of new technology releases so far should only have spent around $15,066,373 on their last wildly successful PDA design. Assuming the design took a year, with the industry norm slipping into the thirteen-month bracket, overall cost will be more than $1,255,531 per month.

The 2001 Design Automation Conference (DAC) made staying abreast of innovation, and availability, a much easier proposition. Even the informal hallway discussions about the new IC Implementation Tool Set gave last year's participants inside information on which vendors actually had them, and which vendors only promised them. Participants went back to work with the confidence to get started upgrading and integrating the new tools into their design flow.

This year's hallway discussions will center around new ideas for the Intelligent Test Bench, bringing things back to the original question: "Can you afford not to go to DAC 2002?" It won't cost you $1.2 million to attend, but it may if you don't.

Gary Smith is chief EDA analyst at Gartner/Dataquest.