Behind The News

Behind The News
Behavioral languages
To no one's surprise, there is increasing talk, if little action, on the question of yet more abstract languages for describing systems. The theory is that if designers made a huge jump in productivity by describing designs textually in RTL rather than drawing them as gate-level netlists, then we should be able to make another much-needed gain by describing the desired behavior of the design in some suitable language, then just compiling that into an integrated hardware/software system.

There are several sticking points to that argument, mostly hidden behind the word "suitable." People coming from a computer programming background-that is, most EDA tool designers-have trouble imagining why C++ isn't the obvious choice. Chip designers tend to buy into some form of the argument that if RTL was good enough for my previous design, then some extension of RTL should be about right for describing system behavior.

But at this point the more theoretically oriented architects start to ask mean questions.

We have already severely constrained the solution space, they point out, by adopting RTL as the assumed structure of all digital systems. Does it make sense to apply that constraint to the domain as well, by requiring that all system behavior be modeled with the same formalism? For that matter, why would anyone think that a language created to generate assembly code for the PDP-11/70 is suitable for describing the behavior of systems?

Such thoughts have led to some research into the underlying problem of actually describing behavior, as opposed to cramming behavior in between registers or writing C programs about it.

There are general approaches, such as Rosetta, and application-specific approaches. Given that constraining the domain of a problem almost always makes it easier, it's a good bet that the latter will bloom earliest.

One such exercise comes from Marlborough, Mass., vendor Novilit, which has created a formal language for describing communications protocols. President and CEO Axel Tillmann describes it as a correct-by-construction language for describing transforms applied to bit streams.

The language has a number of uses, Tillmann said. One is simply to give a compact, unambiguous grammar in which to write protocol standards, so that implementers can figure out what they are trying to do without reading a 400-page specification. A closely related use is to capture existing standards and massage them into the formalism-a task for which Novilit provides tools.

The more dramatic use is to provide a formal language for synthesis. Novilit plans back-end tools that will facilitate partitioning of a protocol description into components and compiling hardware and software to implement them, bypassing the process of manual translation of specs into RTL and C. In fact, Novilit claims several remarkable successes in this process for its early customers.

Data flow description
Another approach to the issue of behavioral synthesis seems to be emerging in a related area. Not unlike Novilit, British vendor RadioScape provides an application-specific tool for capturing intent-in this case, the architecture of Layer-1 baseband modules in communications systems. The tool models the baseband design in terms of interconnected, parameterized modules that can then be extracted at a number of levels of abstraction, including bit-accurate C for detailed simulation or delay models for performance estimates.

The rub is in finding a way to implement the blocks once the architects have explored their design using the various simulation models. To this end RadioScape has acquired Systolix, another British venture, which produces a field-configurable signal-processing array product. The company has announced that the Systolix core will be available as synthesizable or hard-core intellectual property for inclusion in systems-on-chip. The RadioScape modules can be synthesized directly into the Systolix core, providing a direct architecture-to-implementation link for the hardware portion of the baseband system.

A similar possibility is available with yet another new arithmetic-array product, this one from Elixent. The array, based on technology spun off from HP Labs, is populated with 4-bit ALU/register slices and an elaborate, flow-oriented interconnect scheme. Elixent describes the architecture as a fabric on which you can draw data flow graphs.

By choosing a very narrow application area, RadioScape has reduced a nasty problem to a data flow description, without the misdirection of a control-oriented programming language. Configurable arrays of various kinds can be effective at implementing data flow graphs that have been cleansed to control flow complexities. This may be a pattern we will be seeing more frequently, especially with a new generation of gate-arraylike products now emerging that are similar in structure to the Elixent and Systolix arrays, but at a simpler level.

Gate arrays redux?
This next generation of fast-turnaround ASIC products is combining ideas in an interesting way. In effect, the devices are gate arrays-ASICs in which the underlying logic array has been fabricated up to the top couple of metal layers. The wafers are then put on the shelf. A customer design gets mapped into the top layers of interconnect, the final couple of mask steps are done and the wafers ship within a week or so of tapeout. You get fast turns and low NRE, since the only thing the customer is buying is a couple of masks and some standard-product wafers. And you get nearly the performance of cell-based ASIC designs.

That was the theory behind sea-of-gates gate arrays. But as cell-based designs became easier and quicker to do, and as FPGAs took over the slower, lower-density low-volume applications, the gate array was nearly squeezed out of the market. With a couple of exceptions, by the end of 2000 the technology was reduced to just FPGA conversions.

But in an odd way, that retreat laid the groundwork for a major offensive. As the market narrowed, the developers of the base wafers began to ask if it wouldn't be better to give up on the sea-of-gates architecture and just duplicate the logic cell arrays of the FPGAs themselves. That would make the logic mapping for conversion much simpler.

One vendor in fact did exactly that. But others, notably QuickLogic and Lightspeed Semiconductor, created simple, FPGA-like logic cells that included LUT, flip-flop and multiplexer resources but were not carbon copies of any particular FPGA. Designs mapped into these parts, in which hard metal replaced the programmable interconnect of the FPGAs, ran considerably faster than in the programmable devices.

The surprise came when designers looked at implementing non-FPGA designs in these parts. It turned out that the same thing has happened to the cell-based ASIC in deep submicron that FPGAs have lived with all along: Interconnect has become the dominant factor in delay. And just as this fact made a complex logic cell much more efficient for FPGAs, it has also made a complex logic cell more efficient for cell-based designs-enough to make a gate array based on logic cells rather than individual gates a serious rival to cell-based ASICs in performance and density.

The realization that complex logic cells made sense with metal-mask interconnect probably cropped up first at a Chip Express research team about five years ago. But the last few months have seen a flurry of similar ideas, from AMI (also a big FPGA-conversion player), eASIC (an embedded configurable-logic IP vendor and Chip Express spin-off) and, most recently, gate-array stalwart NEC. All are suggesting complex-cell, mask-configured architectures in which the last couple of metal layers configure and interconnect the logic cells. And all are aiming at the gap between FPGAs and cell-based ASICs. Even Lightspeed is said to be eyeing the general-purpose ASIC market.

With the exception of eASIC, these vendors are mum about the exact composition of their logic cells and their allocation of interconnect. But some common threads are appearing.

All of these designs seem to use a combinatorial/sequential cell. Many of them embed clock distribution, power distribution and test circuitry in the lower layers, so users don't have to spend their precious two layers of metal or their logic cells on these infrastructure issues.

One of the most difficult problems in transferring a cell-based design to an FPGA is embedded memory. The new mask-programmed array devices are addressing it the same way the FPGA folks do: by embedding various sizes and shapes of RAM blocks in the base arrays and making those blocks configurable. At least some of the architectures can also convert logic cells to tiny RAMs for assembling small memory instances within the array. But aiming for the middle of the ASIC market, these parts are likely to encounter customer designs rich in memory instances, and have to struggle on the issue even more than FPGAs do.

By bringing near-cell-based density and performance to a quick-turnaround device with low NRE, these chips look well-positioned to plug a big need in the ASIC market.

http://www.isdmag.com

Copyright 2002 CMP Media LLC
5/1/02, Issue # 14155, page 10.