Lies, damn lies and Synplicity

Lies, damn lies and Synplicity
Two years ago, Jason Ware, a Synopsys field engineer out of Dallas, gave me a copy of his 113-point synthesis checklist. I put it in the DeepChip.com download library so other designers could use it. So far, so good. That was until John Gallagher of Synplicity ASIC marketing used Jason's checklist as the basis of a Synplicity net seminar. Synopsys is so complicated, you need a 113-point checklist just to use it. But with Synplicity, ASIC synthesis is just seven easy steps. Only a fool would waste his time learning all those Synopsys synthesis switches. Right?

First off, Synplify Pro has a 312-page user's manual and a 798-page reference manual. In those 1,110 pages you'll find documentation for 21 different directives, 63 attributes, 59 timing constraints, 23 ctrl shortcuts, 20 file commands, seven header/footer variables, 34 edit commands, 41 view commands, 10 Tcl commands, plus a few "hundred" other menu tasks. Just one of these Tcl commands alone, set_option, sets 45 different options. You use all of this by wading through a maze of menus, making custom scripts and embedding lots of directives and attributes in your RTL source code. Clearly, Synplicity is not all that easy to use.

Second, entrusting Synplicity to synthesize your ASIC is like having McDonald's cater your daughter's wedding. You may think you'll get the job done for less money, but you'll pay for it in the long run. Don't get me wrong. Synplicity's done quite well in FPGA synthesis. But you can't just "supersize" an FPGA tool and expect it to work as an ASIC synthesizer. Too many of the things that you fret over in ASIC design aren't in FPGA design.

What about static-timing analysis? When was last time you stitched a scan chain or did ATPG for an FPGA? Clock tree design and skew are life or death for ASICs. Not in FPGAs. I don't care what Synplicity marketing says, you will have to partition that 500k-instance ASIC. And your physical hierarchy will differ from your logical hierarchy. Power analysis is an ASIC issue; it's barely thought of in FPGAs. You don't deal with congestion issues in FPGAs like you have to with ASICs. Crosstalk, electromigration and signal integrity simply aren't FPGA issues. Is this really a happy little seven-step cakewalk? Come on now! Do I honestly look that stupid?

John Cooley runs the E-mail Synopsys Users Group (ESNUG), is a contract asic designer, and loves hearing from engineers jcooley@theworld.com or 508-429-4357.