Dense FPGAs offer platform for apps

The most significant development in programmable-logic technology is the emergence of the programmable system-on-chip. These reconfigurable, system-level devices, now available from a number of FPGA vendors, include both hard and soft microprocessors.

Chip companies have different definitions and names for these technologies, causing some confusion in the market. Altera defines its "SOPC" (system-on-a-programmable chip) as a chip that combines a large quantity of programmable logic with memory, a processing engine and an additional high-value function that can be hard or soft intellectual property (IP). Xilinx defines its "Platform FPGA" as a programmable-logic chip that integrates a variety of hard and soft IP cores, and whose hardware and firmware can be upgraded at any time.

However these new architectures are described, their hardware and software programmability reduces system development time and enables a single device to be targeted at multiple applications. Designers can optimize their systems throughout the development cycle, taking advantage of unprecedented flexibility to make trade-offs during hardware and software implementation. Such flexibility is in tune with today's consumer-style market dynamics.

Platform FPGAs and SOPC devices are already designed into applications such as high-speed networking equipment and base-stations that require high performance, high bandwidth and the reconfigurability to meet changing standards. The next step forward is to use these system-level chips to produce highly flexible hardware systems-for example, set-top boxes that can be reconfigured over the Internet, offering many capabilities that cannot be achieved in software.

ASIC companies and large semiconductor vendors are also adding programmable-logic cores like those offered by Adaptive Silicon and Actel into system-on-chip (SoC) designs. These efforts are at an early stage and are initially geared toward debugging and lowering the cost of developing application-specific standard-product families. However, this development represents a degree of convergence in the industry, indicating programmable SoC as the way of the future.

The combination of large, complex IP blocks and embedded software on a single chip, along with soaring transistor counts, taxes the capabilities of traditional design methodologies. The design of these chips requires a new degree of sophistication, characterized by deeper, system-level design, concurrent hardware/software design and verification at all stages of the design process.

System-level design tools are needed that guide system designers through hardware and software partitioning in order to facilitate attaching cores and blocks of logic to platforms. But with modern programmable-logic devices, there is a potentially huge divide between what can be put in the chip vs. what can be verified to work. Bridging this gap requires the integration of many pieces of the hardware/software design and verification paradigm: software debugging, event-driven logic simulation with complex IP modeling.

Advanced verification
As the design focus shifts from content creation to the challenges of evaluating, integrating and verifying multiple pre-existing blocks and software components, designers will have to deploy advanced verification solutions, such as co-verification and, eventually, formal equivalence checking. Hardware and software must be designed and verified in parallel, since programmable SoC devices are so large and complex that redesigns in the future will incur even more significant delays than they already do.

ASIC designers who are using MPU cores such as ARM, MIPS and PowerPC already employ hardware/software co-verification to spot system design issues early in the development cycle. Increasingly, these methodologies will be carried over into FPGA design. For example, the Mentor Graphics Seamless hardware/software co-verification tool has been successful with ASIC designers and is now being developed for co-verification of FPGA platforms.

A step function in verification performance-anywhere from 100 to 1,000 times faster-can be achieved by modeling systems in C at the algorithmic level. As with ASICs, FPGA designs in the future will be synthesized directly from C code. Having improved the efficiency of modeling at the system specification stage, there is also a need to improve verification time at the gate-level netlist or post-layout stage. Classical event-driven simulators will not disappear, but formal verification techniques will be used increasingly to verify the functionality of these downstream processes.

Formal verification techniques run between 100 and 1,000 times faster than conventional simulation. Tools such as Mentor's FormalPro product use mathematical algorithms to perform equivalence checking, thereby proving, with little manual intervention, whether the design is functionally identical at the specification and implementation stages.

Using an HDL design methodology that involves synthesis and static timing analysis to verify post-layout performance is the norm for today's FPGAs. For platform and SOPC-type designs, synthesis tools must have the capacity to deal with such large devices. They also must be able to work incrementally on small portions of a design. An incremental flow makes it possible to implement design changes in the most efficient way with a minimal effect on time scales. It is equally important that the physical place and route process is part of the incremental design flow.

Synthesis tools also need to handle a variety of IP blocks in different formats without having to black-box them. Utilizing the contents of IP blocks to calculate critical paths is vital in order to achieve fast, accurate timing analysis of complete designs. If the IP modules do not have a timing model, a shadow effect is created, which can prevent timing analysis on large sections of a design.

Traditional synthesis tools have provided limited insight into how a particular application environment will route-and create delays for-a particular net. To achieve maximum circuit performance, physical synthesis tools must be able to identify the specific routes causing excessive signal delay. More important, once a problematic route has been identified, the tool must deploy solutions to reduce the delay on that net.

For example, Mentor Graphics' LeonardoSpectrum uses a second-pass optimization algorithm that closely integrates synthesis and place and route data, allowing quick and accurate identification of optimal data paths for maximum design performance. For large platform designs, this timing optimization within the synthesis tool needs to be handled automatically, since the sheer volume of back-annotation data precludes handcrafting critical paths. Those that move to these design methodologies first will reap the rewards of getting to market first.