Superlog public domain debut delayed

Pulling back from forecasts he made as recently as last spring, Co-Design president and chief executive officer Simon Davidmann now calls a release by year's end unlikely. "These things take time," Davidmann said.

While technical work is going well, he said, the issue now has become how to protect the language against unauthorized incremental changes and third-party improvements that could fragment it and raise barriers to its use by other EDA vendors.

"This process of opening up the language is something we were a bit naive about," he said. "How we do it needs careful thought."

Davidmann said Co-Design still plans to make Superlog openly available. "It is not our intention to make money from licensing the language," he said. "We do intend to make money from licensing our EDA tools. What has become unclear is how we provide that access [to the language]."

For now, Superlog remains proprietary to Co-Design, and engineers wishing to find out about it must sign a nondisclosure agreement (NDA) to access the language reference manual.

"They have to sign an NDA just to receive a technical presentation on Superlog, because there's some proprietary technology inside there," said Davidmann. "But that's not usually a problem. In these meetings everybody has some proprietary technology they need to protect."

Co-Design (San Jose, Calif.) has developed a Superlog partnership program that includes a number of vendors of EDA tools. About a dozen companies — including Arexsys, Get2Chip, Innoveda and Magma Design Automation — have pledged to support the Superlog language.

Davidmann said that as Co-Design comes closer to completing the technical phase of its language work, the problems with releasing the language have started to loom large. "You can't just publish it on your Web site," he said. "Preserving the standard and interoperability makes things complex."

But he said that work on technical aspects of the language is going well. "We've got a group of people — users, not EDA companies — all helping us take it [Superlog] down the standardization route. Extremely well-known industry people have been involved. For example, they gave us good reasons why Superlog has to be a superset of Verilog. We originally thought we would take the best of Verilog but leave the less useful things out. They've shown us Superlog has to be compatible with Verilog 2000."

Davidmann sits on the board of Accellera, an industry standardization body formed earlier this year by the union of Open Verilog International and VHDL International. Davidmann said Accellera is one possible route to Superlog standardization. Other options might include royalty-free licensing by Co-Design or open-source or community-source licensing of the language.

Although Superlog often gets favorable responses from engineers speaking in forums such as ESNUG, it has yet to build up a large base of users. Co-Design's simulation tools SystemSim and Systemex, launched during the Design Automation Conference in June, also support Verilog, C and C++, as well as Superlog.

Dennis Brophy, chairman of Accellera and director of strategic business development at Model Technology Inc., said that Accellera's architectural language committee is focusing on C and C++.

"We know that in the C area there are a number of companies working to exploit cycle-domain semantics. People from Synopsys and the Open SystemC crowd, from C-Level and from Cynapps have all been in discussions," said Brophy. "Although Accellera will tend to stick with things that have great commercial support and which proprietors can donate, we like to standardize de facto practice."

Asked whether Accellera was a suitable organization to standardize Superlog, Brophy said, "Simon [Davidmann] has been a member of Accellera, and OVI before that, for many years. His desire is to gain some understanding of what makes a standard happen. He's probably in the right place. The question is whether he's there at the right time or whether the time has passed."

Accellera has been interested in subsets and extensions to languages, Brophy said. "If it [Superlog] was Verilog-plus-extensions it could be more easily digestible."

Of Davidmann, Brophy said, "He's going for the brass ring. He wants Superlog to be the next design language."

Davidmann said Co-Design's customers "have kept us focused on 'evolution not revolution' — and have required we work with what they have used in the past. This evolution approach is one of our key differentiators compared to some of the C/C++ approaches, which require all hardware designers to give up their HDL methodologies and have real trouble with their legacy HDL code. With Superlog they can just incrementally add things to their existing Verilog hardware or verification code."

For example, he said, the IEEE is just approving the new Verilog 2000 standard. Since Superlog is a complete superset of that language, "this makes our simulator SystemSim the most advanced in supporting Verilog 2000 features than any other released product. We have many customers using features in Verilog 2000 even before it is completely rubber-stamped by the IEEE."