Verisity preps 'e' as test language standard

Verisity preps 'e' as test language standard
SAN MATEO, Calif. — Verisity Inc. will announce today that it will openly license the "e" language linked to its Specman Elite tool in a move aimed to fend off competition and set its product up as a de facto standard for testbench generation languages. Verisity is also donating a subset of e to Open Verilog International, and ultimately will give the entire language, after further maturing, to a standards body such as IEEE.

Cadence Design Systems Inc. and Mentor Graphics Corp. are the first two licensees of the language, Verisity said, and plan to use it for further development of their respective model-checking tools.

Francine Ferguson, vice president of marketing at Verisity (Mountain View, Calif.), said e has become the industry's testbench generation language of choice and that bringing it to the public should speed vendor efforts in ironing out the rough edges of technologies like model checkers.

Industry observers said Verisity's move is well-timed, calling it a preemptive strike against solutions based on C and C++ that are likely to be introduced in the coming months.

Gary Smith, chief EDA analyst at research firm Dataquest Inc., said Verisity's announcement is largely defensive. In 1998, Verisity owned 77 percent of the testbench generation tool market, Smith said, but new tools based on the nonproprietary C and C++ languages may be eating into that market share.

"It is a brilliant move," said Smith. "They dominate market share and are releasing it as a standard to fend off a competitive threat in the C world. If they didn't do something quick, C-based testbench tools would have snatched market share and Verisity would have been forced to change their language or put a C wrapper around e."

Smith said that Synopsys Inc. is the only other serious competitor with a proprietary language, holding 33 percent of the market. But its Vera tool has not gained enough industry support to enable Synopsys to offer it as a viable standard. "Synopsys doesn't have critical mass and you need that to make a standard," said Smith. Other testbench generation companies in the proprietary space include Chronology, Levitate Design and Synapticad.

What's next?

Smith speculated that with Synopsys' stepped-up efforts in the system-level area and its backing of SystemC over the last year, the Mountain View company might be ramping up to provide a testbench generator based on C or C++.

"In the Mentor and Valid days, the EDA industry learned a very valuable lesson about keeping proprietary formats proprietary," said Ferguson of Verisity. "It may seem like you have an exclusive hold over your customer base, but no tool stands alone."

Ferguson said that testbench generators need to work with the breadth of verification tools: from simulation, hardware-software co-verification and code coverage to formal verification and memory modeling.

"Testbench is the glue that captures your verification strategy and harnesses the power of all the tools in the suite," said Ferguson. "If the testbench can't freely access all of the tools in the verification suite including formal model checking, it is not going to be a very good glue for your verification methodology."

Ferguson said the company is licensing the language for $95,000 to any and all EDA vendors with a few caveats: The licensee must commit to creating a tool that supports e and must give a release date for that tool. Ferguson said LicenseE program participants can use e to develop competitive testbench generators and, as part of the license agreement, each licensee must participate in an e steering committee, which hopes to bring the language to maturity. Verisity is charging an extra $15,000 for upgrades to later versions.

After the language matures and others have successfully developed e-supported tools, the company hopes to offer e to IEEE or another standards body to make it a public standard. "We want to make sure that the semantics of e are correctly interpreted and that there are other tools using it and then we will take the next stop to bring it out to the public," said Ferguson. "Making e a public standard has always been in our road map. We didn't want to make e a standard, we wanted to make e a successful standard, and we felt that timing was critical for making it happen."

For its part, Cadence Design Systems said it will support an e link in its model checker and Advanced Verification Cockpit, while Mentor Graphics will likely use the language for a similar purpose in its yet unannounced model checker. Mentor hinted at such a product late last month when it released its Formal Pro equivalence checker.

Steve Rood Goldman, product marketing manager at Cadence, said the San Jose, Calif., company is going to provide an interface based on the temporal components of the e language to the Advanced Verification Cockpit.

A Temporal angle

"Temporal e will be another input along with Verilog, VHDL and C/C++," said Goldman. "Users of Specman Elite have requested that Cadence provide this path in order to have better access to the model-checking capability within the Advanced Verification Cockpit. Along with HDL and C/C++, e is a good language for specifying queries for model checking. We believe that an interface to e will generate business for the Advanced Verification Cockpit and is in line with the Cadence position regarding open standards."

Actually, said Goldman, Cadence endorses a C/C++ model-checking approach, but has made it its mission to support all major interfaces.

"Today, we provide a good solution for Verilog, VHDL and C/C++," said Goldman. "We also support Synopsys' Vera. And now e joins the range of solutions."

Reily Jacoby, formal verification product line manager at Mentor Graphics (Wilsonville, Ore.), said the company is backing e because it has become the de facto standard. "Users have clearly stated they want a standard specification language for formal tools," said Jacoby. "Verisity has, by virtue of market share, established a de facto standard that can be utilized by formal-verification tools. For that reason we are embracing the e language."

In addition to the LicenseE program, Verisity has also donated the temporal subset of the language to Open Verilog International (OVI) to help that organization's formal-verification subcommittee develop standards for property checking used by formal model checkers, among other tools.

Dave Tokic, manager of strategic relationships, said the temporal subset of e is the part of the language that describes time-related properties. "It includes the definition of events, the definition of required and assumed properties — 'expect' and 'assume' — and a rich set of temporal operators," said Tokic. "The temporal operators can be combined to compose any temporal expression of interest. Such expressions can serve as monitors, properties to be verified and so on. The temporal subset also has formal semantics — it is a temporal logic — and was disclosed to OVI in full."

Vassilios Gerousis, chairman of OVI's technical coordinating committee said e is one of several languages the organization plans to evaluate for property checking.

"The e language is suitable for both formal verification and [as a] testbench simulation language," said Gerousis. "Property-checking tools will require a special language to describe design properties. However, experts in the industry believe that property checking by itself will not be sufficient to verify designs. A mix of simulation and property checking will be the better choice. In this area, the e language seems to provide the best of the two worlds."

Gerousis said the formal-verification subcommittee will examine e and weigh it against a list of requirements to "see if it addresses a large space in this area. E will be one of the languages the committee examines and if no one else provides another language within that time frame, the committee will consider e by itself."

Gerousis said that at the top of the list of requirements will be tools and methodologies supporting the language. "E definitely fits this picture," he said. "Now, with the advent of property-checking tools, it will be a good service for our designers to have one language to do testbench and property checking."

He said if and when the e temporal subset becomes a standard through OVI, no licensing will be required for using the OVI standard.

Users pleased

Verisity's announcement is also receiving praise from the user community. Hiroshi Nonoshita, a member of Canon Inc.'s system-on-chip development department, said making e an industry standard would make life easier for designers.

"Every verification engineer in my group is familiar with e language, and we don't have to learn new languages when we adopt new verification tools," Nonoshita said. "For example, the temporal expression of the e language can be used as properties of a model-checking tool. This is a benefit, as [it means] we can write properties easily when we use model-checking tools."

Another benefit, he said, is that properties written in e can be used for both static verification and simulation. "In the block-level verification, we can use the properties as queries of the model-checking tool," said Nonoshita. "And we can use them as a checker or monitor in the system-level simulation. The possibilities of verification methodology would extend further if the e language becomes a standard language for verification."