Keynoter challenges IC CAD developers

Keynoter challenges IC CAD developers
SAN DIEGO — EDA developers in industry and academia should take new approaches to eliminate "uncertainty" in IC physical design, according to Aart de Geus, chairman and chief executive officer of Synopsys Inc. In a keynote speech at the International Symposium on Physical Design 2000, de Geus also called for better estimation and analysis tools, and for attention to new problems such as inductance.

"Physical design has become radically more important recently," de Geus told the audience of some 200 researchers representing both EDA vendors and universities. EDA in general, and physical design in particular, is crucial to the development of the "new economy" that's taking hold based on telecommunications and the Internet, he said.

But to cope with huge increases in chip complexity, de Geus said, "uncertainty has to decrease monotonically across the design process." That means new physical design tools must forestall "unexpected surprises" that can derail a chip's successful production.

Some of the current problems that generate uncertainty, according to de Geus, include routing prediction, crosstalk noise, power supply noise, large buses, and high-frequency induction. "Many of these can be estimated up front, but are not accurately analyzed until after physical design is done," he said.

"Find the areas of biggest uncertainty and focus on these," he admonished developers. "The value of accurate estimation is extremely high."

Many customers have identified timing closure as their most worrisome problem and as a source of considerable uncertainty, de Geus said. A good top-level floor plan is one place to address this uncertainty, de Geus said. "If you have a bad architecture, you cannot fix it — it's no different than building a house," he said.

With floor planning comes global routing, he noted, and if there are congestion issues at that level, there's no point in continuing.

Concert performance

A second way of reducing the uncertainty of timing closure, said de Geus, is by tying synthesis closely to placement. That's because logical design mandates the levels of logic, and hence the delay, while placement determines the distance between blocks. Thus, he said, one must be done in concert with the other.

But making logical and physical design work in parallel still isn't enough, de Geus said. It's also crucial to address well-known problems like signal integrity and crosstalk. And as feature sizes shrink, he noted, inductance will become a critical issue.

"Finally, after 25 years, inductance is coming back," de Geus said. "With high current, inductance does matter." The combination of shrinking voltages, rising frequencies, and the presence of more parts that are constantly switching will cause serious inductance problems in power and ground wires, he predicted — but not until feature sizes drop below 0.18 microns.

De Geus advocated a design methodology in which one first does a floor plan and top-level route, then implements hard intellectual property, and then runs a quick synthesis of blocks that are not yet fully defined. A detailed synthesis-and-placement step follows. Needed throughout this process is fast yet accurate estimation of deep-submicron effects.

"The hallmark of a good algorithm is not only good results — it's good results over hundreds of different problems," De Geus said. Key to minimizing uncertainty, he said, is narrowing the "spread" or range of possible results.