Building a 6.25-Gbit/s backplane

Building a 6.25-Gbit/s backplane
By Gautam Patel, Signal Integrity Engineer, Connection Systems Division, Teradyne Inc., Nashua, N.H., Bill Beale, Senior Signal Integrity and Systems Applications, Engineer, Accelerant Networks, Beaverton, Ore.

As data rates move to 6.25 Gbits/second and beyond, backplane design becomes an increasingly intricate undertaking. The interactions among every element-the on-chip interconnects, connectors, dielectric material and vias-must be taken into account. A subtle change in any element of the system can drastically affect the end-to-end performance.

A 6.25-Gbit/s backplane reference design, jointly developed by Teradyne TCS and Accelerant Networks, was created from the ground up as a complete system, eliminating design obstacles and signal integrity guesswork. This design utilizes two Accelerant AN5500 five-port, 6.25-Gbit/s backplane transceivers and two Teradyne VHDM-HSD connector systems to demonstrate error-free operation over 32 inches of FR-4. The VHDM-HSD is a shielded, high-density, high-speed press-fit connector system optimized for differential-pair architectures.

The ability to pass multigigabit data rates through a backplane system requires great attention to details previously thought to be irrelevant. The trace width, backplane material, diameter of the plated through-hole (PTH) layer-of which a signal transitions into the backplane-and choice of backplane connector all play a crucial role in determining the success of the system.

The backplane thickness is important because it will determine the amount of PTH stub that will exist between the signal pad and the bottom of the board. This stub acts like a filter at high frequencies. The differential S-parameter measurements show a 20-dB improvement at 6 GHz when looking at a signal routed on the top layer of a backplane with an approximate stub of 0.2 inch (vs. a signal on the top layer that was counterbored and had a stub of approximately 0.05 inch).

The backplane for this measurement was 0.22 inch thick with 22 layers and was built from Rogers 4350. The trace length was 10 inches and the VHDM-HSD connector was used. The frequencies that get filtered out are very much dependent upon the length of the stub. It is therefore important to keep the board as thin as possible-an objective that can be most easily accomplished by using a lower-dielectric material. And because the stub effect becomes more prominent as the frequency increases, it becomes necessary to place the highest-speed signals on the layers with the least amount of stub.

Differential signaling is the preferred method for high-speed backplane transmission. Line width is an important factor in this type of signaling. It is commonly believed that the wider the traces, the better the signal integrity, because wider traces result in lower skin-effect losses. In theory this is correct, but in practical applications there are definite trade-offs that need to be considered when using wide lines.

First, wider traces result in lower signal-routing density, which can lead to more signal layers. Wider traces also require thicker cores and fills, in order to achieve the desired impedance, resulting in thicker boards. So, choosing wider traces to reduce skin-effect losses-a low-frequency effect that doesn't necessarily contribute much to signal degradation-will result in thicker boards with more layers. The answer to this problem is to compromise the trace width. Instead of using 12- or 14-mil-wide lines, lines that are 8 or 10 mils wide are a better option.

Experiments were done using varied trace widths and trace lengths to determine at which frequency and data rate the line widths start to make enough of a difference to merit the impact on layer count and board thickness. The difference in line width from 8 mils to 10 mils starts to make a difference at a 5-Gbit/s data rate and at 10-inch trace lengths. But at 2.5 Gbits/s there was no change from 8-mil line widths to 10 mil. The measurements were done in an FR-4 backplane that was approximately 0.09 inch thick. There were no backplane connectors attached; it was a surface-mount adapter to surface-mount adapter test.

Once the backplane has been correctly designed and the PTH stub effect addressed, the next step to achieving terabit connectivity is choosing the correct backplane connector. Several factors need to be considered when choosing the proper backplane connector: It must be a differential connector; it must have very low in-pair skew and low crosstalk; it must have a relatively consistent 100-ohm impedance through the connector; and it must allow for easy differential routing through the pin field. And all this must be achieved at edge rates below 100 picoseconds.

If the connector meets these requirements, it must also be mechanically robust, field replaceable, cost-effective and have all the supporting pieces such as power modules, guide pins, variable pin heights and so on.

Good design techniques like these are critical to create a 1-Tbit backplane in an FR-4 environment. Other factors to consider include daughtercard stackup, power supply decoupling and routing.

Layered effects
The reference design has 12 layers: four signal layers, six plane layers, and the top and bottom layers used for minimal routing and mounting components. It is essential that the plane layers be "coupled" together, with a ground plane close to each power plane. This maximizes the capacitance between the planes, which minimizes the impedance.

In the reference design, the minimum standard "prepreg" (epoxybased preimpregnated carbon or fiberglass) thickness is used between each power and ground plane pair.

Two voltages are required for the AN5500 transceiver, 3.3 and 2.5 V, where the 2.5 V is further partitioned into analog and digital supplies. The 3.3-V plane requirements are a maximum impedance of 2 ohms to a frequency of 2.5 GHz, and a maximum voltage ripple of 10 mV peak to peak. The analog and digital portions of the 2.5-V plane are connected at a single point at the power supply, and isolated from each other by a ferrite bead. The requirement for both the analog and digital 2.5-V planes is a maximum impedance of 1 ohms to a frequency of 500 MHz. To achieve this impedance, decoupling capacitors are placed below the AN5500, as well as around the board.

The routing of the 6.25-Gbit/s links between the two AN5500 transceivers is 100- ohms differential. Normal differential-line routing guidelines are followed. This means each trace of a differential pair is routed symmetrically and with equal line length, continuous reference planes are kept under and over the strip-line traces, and edge-to-edge spacing is 3x the dielectric thickness between traces of any two distinct differential pairs.

Use of the Accelerant transceiver requires designers to pay attention to the reference clock, terminations, bias resistors and ac coupling. The AN5500 requires an external, low-jitter differential 156.25-MHz reference clock with LV-PECL thresholds. To preserve the low jitter of the clock, the 156.25-MHz reference clock is distributed to the AN5500 through a low-jitter buffer. The reference clock also requires proper termination at the AN5500. The recommendation in the reference design is to place the termination resistors in a Y configuration underneath the AN5500.

The AN5500 has integrated terminations for both the serial and the parallel I/Os. Therefore, no external terminations are needed for either the LVDS I/O or the 6.25-Gbit/s link. The AN5500 requires an external 10-k ohms bias resistor, to be connected between the RBIAS pins, to set an internal voltage reference. To minimize noise both traces must be kept short, so the resistor is under the AN5500.

The 6.25-Gbit/s links must be ac coupled, as the common-mode operating point is different between the transmitter and the receiver. Therefore ac-coupling capacitors are used in series with the differential serial link. These capacitors are placed close to the receive pins. Placing the capacitor near the part eliminates the need for an extra via discontinuity. Also, the parasitic inductance of the coupling capacitor helps compensate for the capacitance on the die.

No errors
Channel quality is a critical parameter in achieving error-free 6.25-Gbit/s operation. The channel-which comprises a line card, a connector and a backplane-must remain 100- ohms differential through its entire length. Traditionally, the connector interface is where discontinuities are largest. However, in the reference design, the Teradyne VHDM-HSD is designed to maintain the 100 ohms through the connector and has the added benefit of shielding each pair to minimize crosstalk.

It is desirable to operate at as low a rate as possible, since backplane distortions and crosstalk increase with the frequency of operation. For a fixed bit rate, four-level pulse-amplitude modulation (PAM-4) utilizes half the signaling rate of binary modulation. The penalty for utilizing PAM-4 signaling is that it requires a signal-to-noise ratio of about 9.5 dB better than binary signaling for similar performance. However, in typical systems the S/N decreases at a rate of about 40 dB/decade, which makes PAM-4 the more robust choice.

The most important feature required to achieve robust 6.25-Gbit/s operation is continuous adaptive equalization. Upon power-up and establishing a link, each receiver of the AN5500 determines optimal coefficients to invert the effects of its channel distortions. The coefficients are sent back to the corresponding transmitter. The result is an open eye at the receiver.

The AN5500 continuously monitors the coefficients while receiving user data and relays any necessary adjustments back to the transmitter.

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