Exploration of the design space for integrated Bluetooth CMOS RFICs

Exploration of the design space for integrated Bluetooth CMOS RFICs
In order to give some perspective to the design problem for a Bluetooth receiver, it is useful to examine the performance required to meet two well-understood specifications: sensitivity and intermodulation level.

Aided by some quick arithmetic, it can be concluded that the RFIC needs to have a minimum noise figure (NF) of 24 dB, and a minimum input third-order intercept point (OIP3) greater than -25.5 dBm. No one would actually design a Bluetooth RFIC to meet the minimum requirements, but this analysis illustrates the fact that Bluetooth requirements are a balance between sensitivity and distortion for a relatively short-range link. Furthermore, the analysis shows that state-of-the-art analog processes are not required to meet basic Bluetooth specifications in an RFIC design, so commercially available CMOS technologies make technical and economic sense.

As an example, a circuit block budget for a receiver front end just meeting Bluetooth requirements could include the following: LNA (18 dB gain, 20 dB NF, 0 dBm OIP3), Image Reject Mixer (18 dB gain, 35 dB NF, 15 dBm OIP3), and IF Channel Filter (18 dB gain, 56 dB NF, 32 dBm OIP3). This demonstrates that individual stage requirements are not difficult to meet for Bluetooth. For instance, a typical CMOS LNA with 18 dB of gain at 2.4 GHz can be expected to achieve a noise figure well under 10 dB, and an output IP3 better than +5 dBm — performance much better than that budgeted in the example.

Options for Bluetooth receivers include high IF (usually dual conversion), low IF, and zero IF. Ideally, the receiver architecture chosen should support full integration in a low-cost CMOS process, and minimize the RFIC and Bluetooth transceiver module complexity and area.

In a high IF architecture, the Bluetooth signal is converted to a frequency much greater than the channel bandwidth. The channel filter operates at a frequency high enough to ensure that no image channel exists within the operating frequency range of the receiver, therefore eliminating any requirement for an image reject mixer.

Because of the high quality factor (Q) required for a 1 MHz bandwidth at high IF frequencies, on-chip filtering in CMOS technologies is not possible. Selecting 110.6 MHz for the IF, and using a widely available, low-cost surface acoustic wave (SAW) filter originally intended for DECT applications, creates a viable alternative.

While robust, the advantages of this approach are offset by the need for a second conversion to simplify on-chip demodulation. Dual conversion architectures generally require automatic gain control (AGC) circuits to function properly over wide input signal ranges, adding to the circuit complexity of this approach. For Bluetooth, the short preamble used in the signaling design requires the AGC to respond quickly (fast AGC) to be of any use, leading to further design complications.

A single conversion to an IF that is only somewhat larger than the channel bandwidth is referred to as a low IF architecture. The low IF approach requires an image reject mixer, since image frequencies exist in the receiver operating frequency range, but the channel filter bandwidth is 10 to 20% of the IF, resulting in lower Q requirements and a filter design that can be realized in CMOS. The lower external component cost provided by an on-chip filter is offset by an approximately 25% increase in RFIC chip area, since several active filter sections are needed to achieve required selectivity. Off-chip filters are possible with a low IF configuration, but no off-the-shelf, low-cost filter is presently available which meets Bluetooth requirements. In addition, low IF architectures require only a limiter stage to handle received signal level variation, so no AGC is required. The limiter design is straightforward at low IF frequencies.

ZIF requirements
In zero IF (ZIF) receivers, also referred to as direct conversion receivers, the RF signal is mixed directly to baseband using an I/Q down-converting mixer. While conceptually simpler than a low IF architecture, substituting less process sensitive low pass filtering for bandpass channel filtering, the ZIF approach requires fast AGC and DC offset correction to function properly. The ZIF approach, when implemented in CMOS, must maintain high 2.4 GHz signal levels to overcome the effects of baseband 1/f noise, requiring more gain at 2.4 GHz than equivalent IF based designs. In addition, the ZIF RFIC must be supported by a baseband IC (BBIC) with dual analog-to-digital (D/A) converters for proper demodulation, since simple slicing will not extract the data stream properly.

Comparison of receiver alternatives shows the expected performance for sensitivity, intermodulation, and blocking level for the different approaches with their respective cost implications. Source: Cadence Design Systems

While there are technical tradeoffs between each of the receiver architectures, from a module cost standpoint, the low IF and the ZIF architectures are preferred in production quantities. And with circuit complexity considered, the low IF option with on-chip filtering, emerges as the optimal approach.

Although there are a variety of different receiver architectures in current production designs, all transmitter implementations rely upon a direct modulation transmitter architecture, avoiding the need for complicated up-converters in the transmit chain. This narrows the selection of applicable modulation techniques to IQ modulators, open-loop VCO approaches, and two-point, Delta-Sigma (Delta-Sigma) PLL modulators.

The IQ Modulator uses a vector modulator structure — essentially direct up-conversion — to create the Bluetooth GFSK modulation. The most common approach requires digital modulation shaping for both I and Q channels, and two D/A converters with simple data reconstruction filters to drive the IQ modulator. This modulation technique is the most complex, and adds the most area to the RFIC, since it does not reuse any of the other frequency control elements in the Bluetooth radio.

In open-loop modulation, the RF oscillator is first locked to the transmit frequency with a PLL, and then the PLL loop is opened, allowing the VCO to run free. The modulation waveform is applied directly to the VCO to generate the GFSK signal. Modulation shaping can be done either digitally or with an analog active filter. This technique is generally the least complex.

Three main modulation alternatives are compared: the IQ modulator, open-loop VCO and the Delta Sigma (DS) modulator approach . Source: Cadence Design Systems

The two-point, Delta-Sigma PLL modulator uses a digitally generated analog signal to modulate the VCO and the frequency resolution of a Delta-Sigma Fractional-N controller, in order to cancel the modulation in the frequency divider. The average frequency of the modulated carrier remains locked to the reference crystal frequency, resulting in stable transmitter frequency. The modulation itself does not depend on the PLL bandwidth, so predistortion is not necessary to compensate for PLL bandwidth effects. All modulation shaping is done digitally. This approach reuses much of the PLL circuitry to create the modulation, and qualifies as a moderately complex approach.

Weighing options
The open-loop VCO approach is the most attractive in terms of complexity and cost, but the frequency drift inherent to the technique makes good performance difficult to achieve. Of the low-drift performance options, the IQ modulator requires complex circuitry, relatively high operating currents, and significantly more chip area. The Delta-Sigma modulator approach is the preferred option, as it provides good performance with relatively small investments in current consumption, complexity, and chip area.

Based on the preceding evaluations, it is clear that to mitigate sub-circuit complexity, minimize cost, and enhance manufacturability, a low IF receiver with on-chip channel filter combined with a Delta-Sigma PLL modulator is the best approach. Engineers at Cadence Design Systems have implemented designs using this architecture in 0.25 mm and 0.18 mm CMOS.

Integrated test capability adds value to any IC design, but is especially important in a Bluetooth RFIC. Our approach, time-tested over a wide variety of products, reserves two package pins for an Analog Test Bus (ATB) interface. These pins support a wide variety of single-ended and differential signal measurement and injection configurations using a switch matrix composed of digitally controlled CMOS transmission gates. Using this switch matrix, internal nodes can be measured at key low frequency test points: mixer output, IF filter output, limiter output and VCO tuning voltage. The switch matrix can also be configured to inject test signals: VCO control voltage, IF filter input signal and limiter input signal. ATB control is provided by the particular serial control interface used in the RFIC, which allows access to special test registers. These test points are critical to debugging problems with first silicon.

Selecting a cost-effective package that supports RF integrity is another critical design decision for a Bluetooth RFIC. A candidate package should offer low bondwire parasitic inductance and an effective ground for the die. Packages providing ground downbonds directly to a paddle structure along die edges have proven quite effective.

Since layout drives performance, the need for proper floorplanning as part of the design process cannot be overlooked.

Our approach to the chip floorplan uses a three-column structure set by the dominant filter arrays: the channel filter, the demodulator filter, and the PLL loop filter. The LNA input should be centered along the die edge at the top of a column to reduce bondwire inductance and signal attenuation and to facilitate the ground connection. A short connection to the mixer would follow with the signal progressing through the two columns of the RX chain, with the slicer output placed 90 degrees from the LNA input. The VCO can be co-located near the mixer and the power amplifier (PA), taking advantage of the fact that the RX and TX sections never operate simultaneously. Likewise, the PA output should be centered along a die edge with the rest of the transmit chain in a single column atop a central digital block for the entire chip.

Approaching the RFIC layout in this way minimizes interconnect parasitics and high frequency coupling issues. Additionally, large ground buses can be shared among the RF blocks. With this general outline, the analog pins can then be grouped apart from the digital pins (with digital inputs separated from outputs) to preserve signal integrity and for ease of printed circuit board layout. Taking care to segment power domains during the RFIC layout process minimizes cross-coupling between digital and analog signals.

CMOS implementation comes within the parameters for Bluetooth receiver performance. Included here are the Bluetooth module requirements, the requirements to the input of the RFIC for a typical design, and the performance for the Cadence implementation in 0.25 mm CMOS. The assumed insertion loss used in translating Bluetooth module receiver requirements to the RFIC input is 3 dB. Source: Cadence Design Systems

The full version of this article, "RF and Analog Design Considerations for Fully-Integrated Bluetooth CMOS RFICs" was presented at the Communications Design Conference last month.