Oxide isolation ramps next-gen process

Oxide isolation ramps next-gen process
Roughly every two years for the last decade and a half, a scaled CMOS technology generation has been introduced with about 70 percent smaller linear dimensions than its predecessor and transistors approximately 30 to 40 percent faster. At present, the leading technology in production is the 130-nanometer node. It will be followed by the 90-nm node in the first half of 2003 and by 65-nm technology in 2005.

In addition to straight CMOS scaling, a number of technology enhancements have been under consideration. Silicon-on-insulator (SOI) technology has been under consideration for the last three decades. Four years ago, IBM introduced SOI as part of a mainstream 220-nm CMOS technology used in fabrication of server-type microprocessors. With 174 million transistors operating at 1.3 GHz, the Power4 microprocessor is fabricated using 180-nm CMOS SOI technology.

As CMOS scaling moves from the 180- to the 90-nm node, SOI offers capability with scaling: The channel doping of the MOS device has been increasing to improve the short-channel effects. Increased channel doping results in a significant rise in perimeter-junction capacitance, and lower performance. Thinning the SOI in every generation makes it possible to "cut off" the perimeter-junction capacitance, increase the channel doping for better short-channel effect and boost the device performance.

For IBM's 90-nm technology node, the film thickness is at 50 nm and is projected to go lower for the future generations.

In addition to high-performance CMOS, technology elements for system-on-chip applications have been demonstrated on SOI, some with unique enhancements compared with the bulk technologies. In RF CMOS, in addition to high fT FET (> 200 GHz), one can obtain very high-Q inductors (> 40) using very high-resistivity (>1-kW-cm) substrates.

IBM researchers recently reported on a vertical silicon germanium bipolar transistor on thin SOI with very high breakdown voltage. This bipolar transistor can be easily integrated with CMOS technology. Embedded DRAM has also been shown on patterned SOI.

As the scaling moves to the 90-nm node and beyond, challenges arise in scaling the transistor. Lithography has been the enabler here. Other elements required for scaling: thinning the gate oxide and increasing the channel doping to improve the device's short-channel effect, required to make the smaller device operate properly. Thinning the gate oxide has made it possible to operate the transistor at the lower voltage and shorter channel length.

For the 130-nm technology node, the gate oxide is about 1.3 to 1.5 nm. At 90-nm node and beyond, not only is it difficult to reduce the gate oxide below 1 to 1.2 nm, but there is significant leakage through the gate oxide. Inability to thin the gate dielectric will slow down the scaling of the transistor.

In order to reduce the FET channel length, it's necessary to increase the channel doping. Doing so reduces the mobility and the device performance. Inability to scale the FET gate oxide much beyond 1 to 1.2 nm, and ever higher doping in the FET channel, are the two major barriers to further scaling at 90 nm and beyond.

The strongest case for adopting SOI is to support CMOS scaling to the 90-nm node and beyond. The challenges in "simple bulk" device scaling (oxide and doping) are apparently factors in driving early use of strained silicon. Implementing strained silicon on SiGe is extremely challenging on bulk CMOS: As one increases the strain in the top Si film, the defects in the silicon increase. SOI without strained Si can be viewed as an alternate path for enhancing bulk-CMOS performance and overcoming its limitations. Moving beyond a simple SOI structure, SOI will enable highly strained Si. Indeed, implementing strained Si on SiGe on oxide-known as SGOI-results in either a much lower number of defects or a higher strain level in silicon at a given defect density.