News & Analysis
Testable SoCs
7/18/2002 8:27 AM EDT
Testable SoCs
How systems level considerations impact cost-effective Gigabit Ethernet PHYs
Test flow speeds up MP3 decoder development to eight weeks
Testing the HyperTransport PHY core
Every new design is an ESD test chip
Design for testability: separating the myths from reality
Designers confront speed, complexity issues
For much of the lifetime of digital IC engineering, testability has been one of those issues that was somebody else's problem. But with the arrival of the SoC, it has become clear that testability rests squarely on the shoulders of the design team. If it's postponed until late in the design flow, even, the odds of problems skyrocket.
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