Sandcraft shrinks cache size to cut CPU cost

SAN MATEO, Calif. — Under pressure to reduce bill-of-materials costs, Sandcraft Inc. has rolled out a 64-bit MIPS processor that sells for less than half the cost of an existing device with the same nominal performance, the company said.

To cut the cost of its SR71040A compared with an existing design, Sandcraft said, it unloaded some Level 1 and Level 2 cache memory and removed the Level 3 cache tag completely, allowing more processor die to yield per wafer.

Cache memory took up 75 percent of the die area in the company's existing SR71010A, the architecture on which the SR71040A is based. After making the changes, the cache size now amounts to less than one-third of the die area.

The 128-kbyte, four-way set associative L2 cache of the SR71040A is a fraction of the 512-kbyte, eight-way set associative configuration of the SR71010A. The L1 cache of the SR71040A was also reduced from 32 kbytes (four-way) for both the instruction and data to 16 kbytes (two-way) apiece.

The bottom line: The SR71040A sells for $50 in sample unit quantities compared with a sample price of $135 for the SR71010A running at the same 600-MHz clock frequency.

"CPU performance per dollar is becoming a critical metric for CPUs," Sandcraft's president and chief executive officer Paul Vroomen said. "The metric has been around a while but it was No. 3 or 4 [in customers' selection criteria]. Now it's one of the key selection parameters even in the high-end performance space."

Vroomen said he expects the device to find a home in applications that don't require large data sets. These include low-end enterprise LANs, storage-area networks and office automation equipment such as laser printers. For those systems, the SR71040A still has "substantial cache depth" to prevent pipeline stalls, he said.

"High-end networking likes large caches because they offer a substantial number of services like quality-of-service filters, security and billing services," Vroomen said. "As you go to lower-end systems, they don't typically use these large data caches. Clock speed is a much more critical measure of performance."

Sandcraft was also able to lower costs by packaging the latest device in a 256-pin tape ball grid array instead of the 304-pin ball grid array used by the SR71010A.

To maintain the same clock speed as the SR71010A, the newest device is based on the same superscalar, nine-stage pipeline and manufactured using an equivalent 0.15-micron process technology from Taiwan's United Microelectronics Corp. Later this year Sandcraft plans to field a CPU based on 0.13-micron design rules running at 800 MHz, Vroomen said.