Backplane speeds pushed to 1Tbit/s

These higher speeds increase the sensitivity to dielectric loss and skin effects, resulting in dispersion or interference of adjacent symbols, and so far have ruled FR4 out of such designs.

And the use of better materials does not even solve the problems of the signal to crosstalk ratio. But by using careful design and standard materials and connectors, a terabit version is possible.

Using a 24-layer PCB, the team constructed a 5.58mm thick backplane with 12 ground layers, eight signal layers and two power planes, and created a 12U chassis with 16 slots.

These handle two CPU cards, two switch cards and 12 lines cards, each with a 80Gbit/s bidirectional link to a switch card with more than 40 differential pairs up to 17cm long on the backplane. This gives a maximum bandwidth of 1.2Tbit/s, with the switch cards handling 500Gbit/s each.

The thickness of the backplane is vital as this determines the lengths of the partial through hole vias that act as stubs and filters at such high frequencies. So it is vital to keep the board as thin as possible, but still get enough layers for the backplane connections.

As differential signals are used, the line width is also important. Instead of 12 or 14mil wide lines, the team used 8mil tracks.