Passive filters upgrade jitter testing

The data rates of high-speed serial communications have increased to the point where many communications designers are implementing multilane serializer/deserializer (serdes) I/O architectures on their highly complex systems-on-chip. Taking such an approach maximizes the use of limited pins on these devices while enabling ultrahigh bandwidths at data rates beyond 2.5 Gbits/second for high-speed communications protocols such as Ethernet, Sonet, Infiniband, Fibre Channel and so on.

But as speeds rise, jitter is becoming a growing concern, especially for the multilane I/O cells packed closely together on the system-on-chip (SoC) substrate. Generally, jitter is defined as the variation of a time difference between two threshold-crossing events. There are three major sources of jitter:

• - Electrons scattering within the silicon structure create a background-level or "white" noise.

• - In electrical circuits such as ICs, and especially high-density SoC devices, variations in circuit performance driven by noise or slight changes in reference voltages cause jitter. So does electrical coupling from nearby circuits.

• - ICs are also subject to data-dependent jitter. As data rates increase, the high-frequency content is subjected to two phenomena, depending on the material conducting it: skin effect and dielectric losses. That means the higher-order harmonics in the digital signals will propagate at different speeds down a pcb copper trace or through a connector. In the case of binary data signals, the waveform of fast-toggling bits will see a different delay than a waveform caused by long sequences of consecutive 1s and 0s. Combinations in between will produce varying results. These differences in delay cause different transition times, leading to data-dependent jitter.

Out-of-band jitter becomes especially pronounced when serdes I/O cells are embedded into large digital SoC devices. This is due mainly to power/ground bounce and crosstalk from the digital portion running at several hundred megahertz — compared with phase-locked loop bandwidths of only several tens of megahertz. The transmit PLL is very sensitive to ground bounce and crosstalk, translating it into high-frequency jitter that is out-of-band to the receiver's clock-recovery unit of the link partner. As a result, the received data still contains jitter whereas the recovered clock does not.

It is difficult to assign a quality level to a high-frequency communications IC, or to ensure its compliance with communications standards, without being able to test for jitter tolerance. Given that many ICs now have high-speed communications interfaces operating asynchronously and in parallel, coupled with the fact that many designs require at-speed testing of all interfaces, the challenge for test looms large.

In developing a test solution, the first consideration is to ensure that the test platform is "quiet." This means making sure the tester itself is not a source of an appreciable level of jitter. Careful attention should be paid to minimizing jitter in the physical test setup as well as ensuring the overall quiet test environment is quiet — especially with the device-under-test fixturing and load board. Since all load board traces will contribute to data-dependent jitter, they must be laid out to be as short as possible within a controlled-impedance environment. This will go a long way toward eliminating any jitter within the test environment.

With that said, during the characterization phase comprehensive serdes I/O characterization is possible using a mix of automatic test equipment with hybrid benchtop instruments and sophisticated jitter-analysis tools. The combination delivers the detailed characterization designers need for determining if the SoC's I/O circuitry is within the exacting specifications for jitter as described by the particular communications standard.

Using the results from this thorough characterization, the designer can then determine the parameters to be used in production test. The goal is to establish a set of parameters that closely correlate to the characterization effort. This will ensure that parts that do not meet the jitter specification are flagged in production test, while good parts pass.

Production testing can be accomplished through loopback testing — a simple cable connection between transmit-out and receive-in. This is possible because the multilane serdes interface typically operates in a full-duplex mode by providing transmit and receive functionality at the same time. The loopback can be combined with on-chip built-in self-test (Bist) techniques and on-chip bit-error-rate testers to generate realistic traffic and to provide fast, low-cost, at-speed functional test.

Just using a loopback test combined with on-chip Bist, however, has limitations with respect to jitter, on both the transmit and receive sides. Implementing a pure loopback — nothing more than the cable connection — does not challenge the receiver with respect to jitter and attenuation tolerance, nor does it test the transmitter for jitter generation. What is needed is a simple, cost-effective way to support jitter testing during production test.

Considering that many communications companies outsource the manufacturing and test of these SoC devices, the tests need to be fast and easy to perform. At the same time, the jitter tests must be correlated to the tests performed during characterization to ensure the utmost accuracy and conformance of the design to communications standards.

It is possible to use external signal-generation equipment to provide the coverage needed for jitter testing, but that is too expensive and too slow for the production test of high-density SoC devices. Another option is to place active circuitry directly on the load board. Active circuitry, however, requires calibration and adjustment, and great care must be taken to ensure that the power supply to the circuitry is not injecting any uncontrolled jitter. For small port counts, active circuitry can be used, even though the complexity of the load board layout soon becomes an issue.

A recently introduced technique for production jitter test enhances the simple loopback I/O test by using passive filters to inject data-dependent jitter in a way that is comparable to the effect of a realistic transmission medium for a high-speed data transmission link. By inserting such filters in the loopback path of a serdes multilane interface, it is possible to perform data-dependent jitter screening in production efficiently and at low cost.

The passive filters can be designed for a precisely controlled jitter-injection amplitude at a given data rate, delivering a high degree of correlation with the jitter tests performed during the characterization phase. In addition, the injected jitter is realistic because it is controlled through the run-length variation of real-life data patterns.

This test methodology allows testing jitter generation as well as jitter tolerance with an at-speed functional test in one shot; it also makes it possible to examine high-frequency out-of-band jitter tolerance. The calibration of the technique and the load board design are straightforward. Moreover, no power supply is required, making it easier to deploy and eliminating a potential source of extraneous jitter.

As communication data rates continue to escalate, more SoC devices will undoubtedly incorporate gigabit-speed serdes interfaces. Jitter will become a more pressing concern as designers and test engineers seek to uncover and minimize this threat to I/O performance in their next-generation ICs. We expect to see more efforts around developing cost-effective, reliable ways to effectively test jitter in both the characterization and production arenas.