EPCI-X upgrades path for legacy ISA

CompactPCI has become popular lately. But for all its mechanical and electrical features, including hot-swap, vertical seating and good cooling characteristics, it's not a good choice for many applications. For one thing, its form factor renders desktop PCI boards unusable in the CompactPCI rack. So it's more expensive. Also, it doesn't provide power management capabilities.

Meanwhile, developers have been demanding processors that support simplified, embedded PCI designs that reduce both power and board space needs.

The overwhelming majority of embedded systems continue to use the ISA bus to transfer data. But the latest chip sets do not have native ISA bus support, so new ISA applications can be supported only through the addition of an extra chip. The extra components, extra complexity and extra time needed to design for two bus architectures make the shared PCI-ISA bus architecture burdensome and expensive.

So the embedded systems industry has been moving away from ISA and the demand for efficient data transfers has led to the development of backplanes that use the PCI bus.

But how can board-level solution providers continue to service legacy ISA systems? The solution lies in the ePCI-X specification, which provides an upgrade path for legacy ISA enclosures. EPCI-X is an open standard developed by the PCI Industrial Computer Manufacturers Group (PICMG) to promote the efficient use of PCI and provide a migratory path for legacy ISA systems.

The X addendum to the PCI 2.2 specification defined how single-board computers could support a 64-bit bus at speeds up to 133 MHz. With ePCI-X, I/O bandwidth can be as high as 1 Gbyte/second on each bus when 133-MHz PCI-X is used.

An ePCI-X system is composed of a backplane and a removable CPU board called the system host board (SHB). An ISA (or PCI-ISA) enclosure can accept an ePCI-X backplane and SHB without modification.

The backplane can have up to two PCI buses. Each bus can handle four PCI slots spaced 0.8 inch apart. More slots can be handled if PCI-to-PCI bridges are used. Figure 2 below shows a dual-bus backplane with four 5-volt, 64-bit PCI slots on each bus. The SHB slot is in the middle of the backplane and uses standard, low-cost, widely available PCI connectors.

The ePCI-X specification also defines an SHB that can come in two form factors. One is the half-size (7.52 inches wide by 4.8 high) with a single PCI bus; and the other is the full-size (13.33 inches wide by 4.8 high or as long as a full-length ISA board) with one or two PCI buses.

The two PCI buses are independent. Each bus is in its distinct clock domain and has its own interrupts and arbitration signals. Bus width (32- or 64-bit), protocol (PCI or PCI-X) and speed (between 33 and 133 MHz) are independent of each other. The interrupt binding is identical to the standard PCI-ISA specification, thereby avoiding any BIOS changes when upgrading to ePCI-X.

A single-bus SHB cannot be used in a dual-bus backplane. However, a dual-bus SHB in a single-bus backplane uses extra signals to detect the number of bus segments (0, 1 or 2) and disable any unused circuitry. Backplanes and SHBs can have 32- or 64-bit buses and all combinations are valid. For example, a 32-bit SHB can function over a 64-bit backplane, and 64-bit add-in cards can do 64-bit peer-to-peer transfers.

An ePCI-X backplane fully complies with the PCI-2.2 specification, with the PCI-X addendum and the ATX 1.0 specification. Expansion slots are provided with 3.3-V as well as the PCI-standard 5-V mechanical keying. Each bus can have different keying.

Backplane variation

The SHB slot is not aligned with the expansion slots. This makes it difficult to put the SHB in an expansion slot or an expansion board in the SHB slot. And instead of 5-V or 3.3-V mechanical keying, the SHB slot uses an independent electrical keying scheme for each bus: when it detects incompatible keying, the SHB stays in reset mode.

While the 2-nanosecond clock-skew requirement of 33-MHz PCI presented few difficulties to designers, for PCI-X the skew window shrank to 500 picoseconds. Backplane variations in trace lengths and trace velocity made this sometimes difficult to achieve.

But tolerances on trace dimensions and dielectric constants are more forgiving in the embedded PCI-X specification. So to target minimum skew and avoid overspecification of the backplane, an ePCI-X backplane should provide a clock feedback trace for each bus. The SHB can use this feedback to compensate for variations between backplanes, thereby providing a lot of freedom to backplane designers. The backplane brings all ATX-compatible power supply controls and +5-V aux supply to the SHB as well as a user-definable signal such as a "door open" alarm. And ePCI-X supports PCI 2.2 power management events with the backplane providing a +3.3-V aux supply.

The SHB does not require an extra trace to be able to turn off the power supply, and power management events from a PCI add-in card or on-board device can turn the system back on. To satisfy the latest PCI ECN, the ePCI-X backplane provides an SMBus link between the SHB and all expansion boards that can be linked to other backplane resources or system cards for monitoring purposes.

Assuming 1 amp per pin, a half-size SHB (P1 and P2 connectors) has enough power pins to draw up to 18 A on the 5-V rail and 16 A on the 3.3-V rail. A full-size SHB draws a total of 25 A on the 5-V rail and 22 A on the 3.3-V rail, providing a total power envelope of almost 200 watts.