Gbit/s net processors challenge system designers, cPCI

Gbit/s net processors challenge system designers, cPCI
The use of high-performance gigahertz, gigabit/second network processor architectures in a CompactPCI form factor is gaining adherents in the single-board computer market because of its combination of performance, low cost and reliability.

But the use of network processors in CompactPCI leads to some unique design issues. One major issue is the transfer of packet traffic to and from the network pin a CPCI chassis. This problem can be solved by using the proposed specification PICMG 2.16, otherwise known as the compact packet-switching backplane. Mapletree Networks' MTN5300 is an example of a CompactPCI card implementing this feature.

Basically, network processors provide system-on-chip solutions, incorporating DSPs, microcontrollers and memory along with network interfaces such as Ethernet (used for Internet Protocol traffic) and Utopia (used for asynchronous transfer mode traffic). All of this functionality is highly integrated, and is available on one or two chips that also provide a tremendous amount of processing power. System-on-chip solutions can simultaneously process hundreds of voice or data calls.

Network processors work at the packet level, but the exact functionality varies. Basic network processors take in circuit-based voice, compress it, packetize it, encapsulate it (usually into IP or ATM) and then send the processed traffic out toward the packet network. This type of NPU is used in media gateways and soft switches. Advanced network processors, such as Mapletree's Access Processor, also provide additional functionality, such as protocol conversion for network interworking or voice quality-of-service features such as echo cancellation and jitter buffering.

By virtue of its high level of integration, a single network processor is capable of processing hundreds of ports. Since network processors are self-contained, and need little other than additional memory banks (usually in the 8-Mbyte range), a single CompactPCI card may have five or six network processors to provide OC-3 capacities (2,016 ports). This capacity represents a wire-line speed of 155 Mbits/s. Compare this to industry-leading cards using separate DSP, RISC and other components, which offer a maximum capacity of around 300 ports.

The idea of having a single card processing a full OC-3 stream worth of traffic may have been unimaginable a few years ago, but it is very possible with the network processors that are available today.

One of the major issues that system designers will run into when using network processors is the intercard bus. Traffic must be moved between cards in a system — for example, between the I/O card and the processing card. The solution for time-division multiplexed traffic is the H.110 bus in CompactPCI, which provides a real-time, high-density bus. However, there is no standard architecture for packet traffic. This is where the compact packet-switching backplane (CPSB) comes into play for CPCI systems.

Since the introduction of CompactPCI, the existing options have sufficed. However, the advances provided through the use of network processors have increased processing capabilities by exponential levels, straining the bandwidth of currently available connection options.

Today's standard connections are limited not only by bandwidth but also by functionality. The H.110 bus by virtue of its architecture is perfect for transferring circuit-based voice traffic between boards, but does not provide a very good solution for other types of traffic. The PCI bus is excellent for transferring control and status information, but does not scale very well as a packet bus.

Other means of connecting cards together do not provide the reliability or open standards that customers expect from carrier-class systems. External connections are not carrier-class compatible, since the exposed wires can be easily damaged or cut. In addition, external connections do not lend themselves to hot-swap applications.

Proprietary connections, meanwhile, bind an OEM to a specific vendor and do not allow an OEM to easily utilize the latest products in the market. They are a barrier to improvement and innovation, a sure death sentence in the fiercely competitive telecom industry.

These limitations gave rise to the development of CPSB, which provides a better method of transferring large amounts of data between cards, with an emphasis on packet traffic. This is because it incorporates three features important in network processor applications: a point-to-point architecture; the use of the standard 10/100/1,000 Ethernet protocol for packetization; and redundancy support.

CPSB's point-to-point architecture maximizes the amount of bandwidth available. And since CPSB is for packet traffic, packets can be easily switched from one card to another.

In CPSB terminology, the processing cards are "nodes" and the centralized interface cards are "fabric." Thus, there are three parts to a CPSB system:

1. A central interface card to terminate incoming traffic (fabric card);

2. A set of processing cards (node cards);

3. Another central interface card to send the outgoing traffic to the network (fabric card).

Since the CPSB standard was designed for packet traffic, traffic can be routed from one card to any other card via the fabric card.

The CPSB standard was designed for 21-slot chassis. A CPSB chassis can support a maximum of two fabric cards and 19 node cards. The standard also includes an optional "extended-fabric" card, which supports up to 24 node cards. The extended-fabric card uses Connector 4 to support extra node cards. However, Connector 4 is also used for H.110 signals. Thus the standard fabric card can coexist with H.110, but the extended-fabric card will conflict with it. Because of this, it is unlikely that telephony systems will use the extended-fabric cards.

There is a full-duplex connection between each node card and the fabric card — two pins for transmit and two for receive, as well as four for ground.

Each node card can connect to both fabric cards. The dual fabric cards can be used as redundancy, or as additional resources. Mapletree's MTN5300 CompactPCI processing card, for example, acts a node card in CPSB chassis.

The use of standard Ethernet as the data link layer is part of the CPCI philosophy of using standard, well-understood technology and adapting it for high-availability, rugged systems. In the case of CPSB, Ethernet is used to transfer traffic between the node cards and the fabric cards. Ethernet was chosen as the data link layer because it is cheap, simple and reliable — the exact reasons that Ethernet is the networking technology of choice for corporate and other networks around the world.

Ethernet also fits in well with network processors, many of which have Media Independent Interfaces for connection to Ethernet.

Through the use of Ethernet, a full set of standards addresses issues in CPSB such as electrical requirements: A compliant CPSB backplane design must meet the IEEE requirements as specified for 100/1,000 Base T Ethernet. Specifically, backplane wiring must meet Category 5/5e cable plant requirements as specified in ANSI 568. The node card and the fabric card use autonegotiation (as defined in IEEE 802.3) to select compatible rates between 10/100- and 1,000-Mbit/s Ethernet.