Scaling down on the wings of a FinFET-DGCMOS

Scaling down on the wings of a FinFET-DGCMOS
The double-gate (DG) FET provides a fundamental advantage over conventional single-gate (SG) FETs. In short-channel FETs the drain potential competes with that of the gate to influence the channel. When the drain 'wins' the transistor is said to suffer from 'punch-through' and becomes too leaky in the 'off' state to be useful for ultra large-scale integration (ULSI). With a conventional transistor the channel potential is isolated from the drain by a combination of proximity of the gate electrode (thin gate dielectric) and the neutral body (shallow body depletion depth).

Double-gate device architecture escapes the intrinsic compromise presented by conventional FETs.

As a result, good short-channel control requires strong coupling of the channel to the body; this coupling has two negative influences, namely increased subthreshold swing, and decreased drive current for a given VGS-VT. In the double gate architecture, a second gate plays the role of the neutral body and thus short channel control can be effected through increased influence of this second gate. Since this second gate is electrically connected to the first gate, increased coupling for short-channel control also results in increased coupling for subthreshold and superthreshold control of the channel.

While enormous progress has been made toward integration of high-k gate dielectrics, significant obstacles persist. As a result considerable uncertainty remains regarding just when these materials will become available. Further TOX reduction is needed to enable continued reduction of LGATE and VDD. Short-channel scaling is superior for double gate FETs if the body (TSI) is very thin and is fully depleted during normaloperation. Since both gates contribute to the control of thechannel, the effective gate control corresponds to that of amuch thinner physical gate oxide than that of a single-gateFET.

The short-channel advantages of DGFETs are directly illustrated below where DGFETs and SGFETs were simulated for minimum achievable LGATE. Significantly shorter LGATE is accessible with DG for either a given TSI or TOX. This is due to increased coupling (in the subthreshold regime) of each gate to its opposite channel.

Simulations compare single-gate (SG) and double-gate (DG) minimum LGATE achievable for a given silicon thickness, T SI.

While the near-ideal subthreshold swing of the DGFET always allows a lower VT than that of a corresponding single-gate FET for the same IOFF, this advantage becomes particularly important in the arena of low-power FETs. For picoampere-scale IOFF applications the DGFET VTmay be 200mV lower than that of the corresponding single-gate FET and can result in as much as 60 percent greater overdrive for the DG case in a low-VDD application.

The trouble with double-gate CMOS Many double-gate devices have been demonstrated over the years but the planar double-gate FET has faced four significant structural obstacles: 1. Self-alignment of the front and back gates to each other, 2. Self-alignment of the back junction edges to the back gate, 3. Low back-gate-electrode resistance, and 4. Area-efficient contact to the back gate.

Each of these issues impede high performance due to substantial penalties in parasitic capacitance or resistance to the device, which threaten to ruin the intrinsic advantages of the device. Hence a significant challenge is presented to the successful implementation of DGFETs in CMOS technology.

A solution to the double-gate challenges is provided by the Delta-device structure, more recently referred to as FinFET. Variants of this structure have been discussed under the names of OmegaFET and Tri-Gate recently. In this double-gate structure, the silicon body has been turned on its side to form a 'fin' of silicon standing perpendicular to the wafer plane. The gate electrode is formed on both sides ofthe fin, allowing simultaneous definition of both gates with a single mask level and etch, thereby solving DG challenge number 1.

Furthermore, since the source and drain regions have both 'front' and 'back' faces symmetrically exposed from the front of the wafer, the source and drain regions may be ion implanted symmetrically to solve DG challenge number 2. The gate electrode resistance and contact issues, — challenges 3 and 4—, respectively,are also favorably resolved. In addition to the benefits of DGFETs, the FinFET provides further opportunity toward higher drive-current density without requiring TOX reduction and its associated leakage.

This can be accompalished by adjusting the height of the silicon fins (HFIN), to be greater than one-half the fin pitch. Increased drive-current density can be attained in this manner to help overcome non-scaling interconnect capacitances associated with thick wires.

The FinFET structure forms channels in a 'fin' of silicon perpendicular to the wafer surface. The gate is formed on both sides.

Progress in FinFET DGCMOS Technology We here briefly summarize some key results recently achieved in FinFET/DGCMOS technology.

High performance (as gauged by CV/I) FinFETs have been fabricated and a comparison of conventional FETs to FinFETs shows that the structure already meets or exceeds the best reported conventional FET performance for a given gate length, with devices demonstrated to gate lengths as small as 10nm. As process advances further reduce parasitic series resistance it is expected that the FinFET performance advantages will grow, particularly for gatelengths below 40nm.

Complete CMOS integration and operational circuits were demonstrated on four-stage inverters in 180nm foundry based CMOS mapped to FinFET design. Physical redesign was achieved with changes only on the active area (silicon) mask layer. Fabrication was accomplished in the same manufacturing facility that runs production 180nm foundry products.

An operational six-device SRAM cell has been demonstratedin 180nm layout rules to achieve a 4.8l-mm squared cell. Thephysical footprint of a planar cell was maintained.

A 61-stage ring oscillator consisting of 60 inverters and a single NAND2 was fabricated in foundry-based 180 nm FinFET CMOS to demonstrate transient operation of FinFET CMOS circuitry. A delay of 19ps was achieved with a 2.2nm oxide and 140 nm gate-length FinFET, operating at 1.5V.

Physical design conversion of planar CMOS circuits to FinFET has also been demonstrated. In the figure below a planar latch design in conventional 90nm CMOS is shown along with the additional mask layers needed to convert the circuit to FinFET/DGCMOS.

A planar latch designed in 90nm CMOS is mapped to FinFET/DGCMOS through addition of two new mask layers.

The FinFET layers were generated by use of design automation tools which place the appropriate numbers of fins within the original active area (silicon) shapes as shown. The fins are defined by Sidewall-Image Transfer Lithography, which places fins on the perimeter of the drawn rectangles (mandrels). Subsequently a trim mask is used to remove undesired parts of loops and a conventional resist mask is used to block off source and drain regions (not shown) to link the fins together. While manual design was required for SRAM cells, conversion by algorithm was able to handle most of the design.

The electrical width of a single fin is given by twice the height of the fin since both sides of the fin contribute to the conduction. Electrical transistor width, WEFF, is thus quantized in steps of 2 x HFIN giving rise to challenges in the design of low-power cells, where narrow devices may require crafting to specific drive strengths. The variation of WEFF is also very different from that of planar CMOS. Since wide FETs consist of many narrow fins, the WEFF tolerance will be a fixed percentage of WEFF for all devices (aside from some improvement from averaging effects on wide devices).

Analog design is affected in various ways by FinFET characteristics. Tracking of device widths is process controlled (HFIN variation) and will thus be superior to that expected from sub-100nm lithography in planar FETs; however, high-precision width control cannot be achieved through the traditionally used method of employing wide FETs. The FinFET body is fully depleted during normal operation and thus so-called history effects are negligible, provided operation in accumulation at high voltage is avoided. Self-heating can be a negative factor when FETs are biased nearby VGS=VDS=VDD.

Finally, passive devices can be readily co-fabricated in larger silicon mesas, patterned simultaneously with the source and drain regions, thereby enabling seamless mapping of many analog functions to FinFET-DGCMOS.

E. J. Nowak, and co-authors B. Rainey, M. Breitwisch and D. M. Fried are with IBM Microelectronics Division, Essex Junction, VT. Co-authors T. Ludwig, V. Gernhoefer, J. Keinert I. Aller, are at IBM Systems Group, Boeblingen, Germany; and co-authors J. Kedzierski, M. Ieong are at IBM T.J. Watson Research Center, Yorktown Heights, N.Y.