SOI and strained silicon complement each other

For the past 25 years, geometric scaling of silicon CMOS transistors has enabled not only an exponential increase in circuit integration density — Moore's Law — but also a corresponding enhancement in the transistor performance itself.

However, as the length of the transistor gate has dropped below 50 nm and the gate oxide thickness has dipped below 1 nm, physical limitations such as leakage current and power density make geometric scaling an increasingly challenging task, impeding the pace of performance enhancements. So to continue CMOS device scaling and trends, innovations, both in device structures and materials, are now required more than ever.

One such structural innovation that has recently been introduced is the silicon-on-insulator (SOI) MOSFET. These transistors provide advantages over bulk MOSFET devices in both circuit speed improvement and channel-length scaling: IBM has been utilizing SOI in CMOS technology since 1999. The main advantage is the decreased junction capacitance, made possible by the presence of an insulating layer under the active silicon region, which leads to reduction of the total capacitive load for the transistor. At the CMOS circuit level, this reduced load can be used to achieve faster chip speeds or a reduction in chip power consumption or both.

Another idea that is receiving a lot of attention in the industry is the introduction of strained-silicon layers into a MOSFET, recently demonstrated in modern CMOS integration by IBM and others. In strained-silicon MOSFETs, the current drive in the transistor itself is improved by using a channel made of a thin (20 nm) layer of strained silicon. To produce strained silicon, the individual silicon atoms in the layer are pulled slightly farther apart than they would naturally occur, resulting in a change in the electronic band structure. The electrons and holes that carry the current in the silicon can now literally move faster in the layer, resulting in higher currents in the transistor that lead to faster circuit speeds.

The SOI MOSFET can be viewed as a device structure innovation, which reduces the amount of current it takes to switch a transistor, while the strained-silicon MOSFET is a material innovation that increases the amount of current the transistor has available for making the switch. These improvements are exactly complementary, so an exciting possibility would be to combine the advantages of strained silicon with the advantages of SOI to achieve maximum chip performance benefits.

In a strained-silicon SOI MOSFET, the buried insulator can drastically reduce the parasitic capacitance, while the strained-silicon channel enhances the current drive of the device. The principles that give rise to the advantages of strained silicon and SOI structures are not expected to interfere with each other since the innovations target two different regions of a MOSFET: buried insulator under the active region and the active channel region itself.

Beyond the performance advantages, there are other synergies for integrating strained silicon and SOI. One is in the transistor junction capacitance and leakage. In most cases, strained-silicon channels are formed on a thick layer of SiGe, so the source and drain junctions of a bulk strained-silicon MOSFET are formed within the SiGe layer. Since SiGe has a lower energy gap and higher dielectric constant, this leads to higher junction capacitances and junction leakage. However, when a strained-silicon channel is formed on an SOI structure, the increased junction capacitance and leakage associated with SiGe are mitigated by the silicon-on-insulator structure, so they are not as detrimental to the transistor performance.

Several structures that form a strained-silicon channel layer on SOI have been reported by IBM and others. Most of the demonstrated techniques involve either epitaxial growth of SiGe followed by layer transfer, or thermal treatment of the layers to create SiGe-on-insulator structures. A strained-silicon layer is then epitaxially grown on the SGOI before CMOS device fabrication. After the strained-silicon SOI substrate has been formed, the rest of the fabrication process can continue nearly unchanged from a normal SOI transistor flow.

With the increasing need to improve CMOS transistor performance without increasing static power and leakage currents, the industry is accelerating the search for new structures and materials. Strained-silicon SOI transistors are clearly a key innovation that extends the performance trend of MOSFET devices and enables further advancement of the silicon CMOS technology necessary for driving the semiconductor industry.

Jeff Welser is director of high-performance logic technology at IBM Microelectronics Division (East Fishkill, N.Y.)